Active Layer Is Group Iii-v Compound (epo) Patents (Class 257/E21.441)
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Patent number: 11552198Abstract: A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.Type: GrantFiled: December 4, 2020Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventor: Durai Vishak Nirmal Ramaswamy
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Patent number: 11468221Abstract: A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.Type: GrantFiled: January 13, 2020Date of Patent: October 11, 2022Assignee: SAMSUNG ELECTRONICS CO.. LTD.Inventors: Jung Ho Do, Seung Hyun Song
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Patent number: 9711614Abstract: A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.Type: GrantFiled: July 1, 2015Date of Patent: July 18, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Jianjun Cao, Sadiki Jordan
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Patent number: 9379247Abstract: A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.Type: GrantFiled: June 28, 2012Date of Patent: June 28, 2016Assignee: CBRITE INC.Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong, Tian Xiao, Juergen Musolf
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Patent number: 9368591Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.Type: GrantFiled: July 18, 2014Date of Patent: June 14, 2016Assignee: GlobalFoundries Inc.Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
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Patent number: 8941118Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.Type: GrantFiled: September 30, 2013Date of Patent: January 27, 2015Assignee: HRL Laboratories, LLCInventors: Rongming Chu, David F. Brown, Adam J. Williams
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Patent number: 8828824Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.Type: GrantFiled: March 29, 2011Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Shu-Jen Han, Ko-Tao Lee, Kuen-Ting Shiu
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Patent number: 8822317Abstract: A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.Type: GrantFiled: September 5, 2012Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Cheng-Wei Cheng, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
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Patent number: 8748274Abstract: A method for fabricating a semiconductor device includes: forming a GaN-based semiconductor layer on a substrate; forming a gate insulating film of aluminum oxide on the GaN-based semiconductor layer at a temperature equal to or lower than 450° C.; forming a protection film on an upper surface of the gate insulating film; performing a process with an alkaline solution in a state in which the upper surface of the gate insulating film is covered with the protection film; and forming a gate electrode on the gate insulating film.Type: GrantFiled: December 17, 2009Date of Patent: June 10, 2014Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Ken Nakata, Seiji Yaegashi
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Patent number: 8598627Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.Type: GrantFiled: November 12, 2009Date of Patent: December 3, 2013Assignee: EPCOS AGInventor: Léon C. M. van den Oever
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Patent number: 8564029Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.Type: GrantFiled: May 20, 2011Date of Patent: October 22, 2013Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
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Patent number: 8541773Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.Type: GrantFiled: May 2, 2011Date of Patent: September 24, 2013Assignee: Intel CorporationInventor: Ravi Pillarisetty
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Publication number: 20130105869Abstract: A method of forming a group III-V material layer, a semiconductor device including the group III-V material layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate; a group III-V channel layer formed on the substrate; a gate insulating layer formed on the group III-V channel layer; and a gate electrode and source and drain electrodes formed on the gate insulating layer, the source and drain electrodes having intervals from the gate electrode, wherein voids exist between a lower portion of the group III-V channel layer and an insulating layer. The group III-V channel layer may include a binary, ternary, or quaternary material.Type: ApplicationFiled: August 7, 2012Publication date: May 2, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-moon LEE, Young-jin CHO
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Publication number: 20130026495Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.Type: ApplicationFiled: April 25, 2012Publication date: January 31, 2013Applicant: HRL LOBORATORIES, LLCInventors: Rongming Chu, David F. Brown, Xu Chen, Adam J. Williams, Karim S. Boutros
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Publication number: 20130017648Abstract: Embodiments of the disclosure provide methods of fabricating a thin film transistor device with good profile control of peripheral sidewall of an active layer formed in the thin film transistor devices. In one embodiment, a method for manufacturing a thin film transistor device includes providing a substrate having a source-drain metal electrode layer disposed on an active layer formed thereon, wherein the active layer is a metal oxide layer, performing a back-channel-etching process to form a channel in the source-drain metal electrode layer, and performing an active layer patterning process after the back-channel-etching process.Type: ApplicationFiled: June 30, 2012Publication date: January 17, 2013Applicant: Applied Materials, Inc.Inventor: Dong-Kil Yim
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Publication number: 20130001657Abstract: A metal oxide semiconductor field effect transistor and method for forming the same include exposing portions on a substrate adjacent to a gate stack, forming a dopant layer over the gate stack and in contact with the substrate in the portions exposed and annealing the dopant layer to drive dopants into the substrate to form self-aligned dopant regions in the substrate. The dopant layer is removed. A metal containing layer is deposited over the gate stack and in contact with the substrate in the exposed portions. The metal containing layer is annealed to drive metal into the substrate to form self-aligned contact regions in a metal alloy formed in the substrate within the dopant regions. The metal layer is then removed.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
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Patent number: 8344421Abstract: Structures and fabrication processes are described for group III-nitride enhancement mode field effect devices in which a two-dimensional electron gas is present at or near the interface between a pair of active layers that include a group III-nitride barrier layer and a group III-nitride semiconductor layer. The barrier layer has a band gap wider than the band gap of the adjacent underlying semiconductor layer. The two-dimensional electron gas is induced by providing one or more layers disposed over the barrier layer. A gate electrode is in direct contact with the barrier layer. Ohmic contacts for source and drain electrodes are in direct contact either with the barrier layer or with a semiconductor nitride layer disposed over the barrier layer.Type: GrantFiled: May 11, 2010Date of Patent: January 1, 2013Assignee: IQE RF, LLCInventors: Xiang Gao, Shiping Guo
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Patent number: 8344425Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.Type: GrantFiled: December 30, 2009Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Marko Radosavljevic, Uday Shah, Gilbert Dewey, Niloy Mukherjee, Robert S. Chau, Jack Kavalieros, Ravi Pillarisetty, Titash Rakshit, Matthew V. Metz
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Publication number: 20120329229Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: ApplicationFiled: September 5, 2012Publication date: December 27, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Publication number: 20120309153Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Publication number: 20120298958Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.Type: ApplicationFiled: August 9, 2012Publication date: November 29, 2012Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
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Growth of group III nitride-based structures and integration with conventional CMOS processing tools
Patent number: 8318563Abstract: A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.Type: GrantFiled: May 19, 2010Date of Patent: November 27, 2012Assignee: National Semiconductor CorporationInventors: Sandeep R. Bahl, Abdalla Naem -
Publication number: 20120280210Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Inventor: Ravi Pillarisetty
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Publication number: 20120248501Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.Type: ApplicationFiled: March 29, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Shu-Jen Han, Kuen-Ting Shiu
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Publication number: 20120248502Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.Type: ApplicationFiled: March 29, 2011Publication date: October 4, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cheng-Wei Cheng, Shu-Jen Han, Ko-Tao Lee, Kuen-Ting Shiu
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Publication number: 20120244674Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.Type: ApplicationFiled: March 22, 2012Publication date: September 27, 2012Inventors: Dong Hyuk Kim, Dongsuk Shin, Myungsun Kim, Hoi Sung Chung
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Publication number: 20120223327Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.Type: ApplicationFiled: May 15, 2012Publication date: September 6, 2012Inventor: Michael A. Briere
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Publication number: 20120187505Abstract: A method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing raised source/drain regions on the source/drain regions, the grown raised source/drain regions including III-V semiconductor material, and growing metal contacts on the grown raised source/drain regions. Another method for forming a transistor includes providing a patterned gate stack disposed on a III-V substrate and having sidewall spacers formed on sides of the patterned gate stack, the III-V substrate including source/drain regions adjacent to the sidewall spacers and field oxide regions formed adjacent to the source/drain regions. The method includes growing metal contacts on the source/drain regions.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Applicant: International Business Machines CorporationInventors: Dechao Guo, Shu-Jen Han, Jeehwan Kim, Kuen-Ting Shiu
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Patent number: 8227359Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.Type: GrantFiled: August 8, 2011Date of Patent: July 24, 2012Assignee: Showa Denko K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
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Publication number: 20120156843Abstract: A dielectric layer for a gallium nitride transistor is disclosed. In one example, the dielectric layer has a hydrogen content of less than or equal to 10% by atomic percentage. In one example, both a dielectric layer formed before a conductive electrode of the transistor and a dielectric layer formed after the conductive elective electrode have a hydrogen content of less than or equal to 10% by atomic percentage. In one example, the dielectric layer formed before the conductive electrode is formed by a LPCVD process and the dielectric layer formed after the conductive electrode is formed by a sputtering process.Type: ApplicationFiled: December 17, 2010Publication date: June 21, 2012Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
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Publication number: 20120119226Abstract: A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.Type: ApplicationFiled: January 23, 2012Publication date: May 17, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Keiichi MATSUSHITA
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Publication number: 20120104473Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.Type: ApplicationFiled: May 20, 2011Publication date: May 3, 2012Applicant: Institute of Microelectornics, Chinese Academy of Sciences a Chinese CorporationInventors: Haizhou Yin, Huilong Zhu, Zhijong Luo
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Patent number: 8158490Abstract: A method for producing a Group III nitride-based compound semiconductor device includes, before bonding a support substrate to an epitaxial layer formed on an epitaxial growth substrate, forming trenches in such a manner as to extend from the top surface of a stacked structure including the epitaxial layer to at least the interface between the epitaxial growth substrate and the bottom surface of the epitaxial layer. The trenches divide the epitaxial layer into extended device areas which encompass respective product device structures, and stress relaxation areas. A plurality of laser irradiations are performed for laser lift-off such that, after each laser irradiation, the expanded device areas and the stress relaxation areas are formed by a laser-irradiated area and a laser-unirradiated area, and a strip-shaped laser-unirradiated stress relaxation area is formed at a boundary between the laser-irradiated area and the laser-unirradiated area.Type: GrantFiled: March 30, 2010Date of Patent: April 17, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiya Umemura, Masahiro Ohashi
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Patent number: 8154024Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.Type: GrantFiled: April 19, 2011Date of Patent: April 10, 2012Assignee: Canon Kabushiki KaishaInventor: Tatsuya Iwasaki
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Publication number: 20120080760Abstract: The present invention discloses a dielectric structure, a transistor and a manufacturing method thereof with praseodymium oxide. The transistor with praseodymium oxide comprises at least a III-V substrate, a gate dielectric layer and a gate. The gate dielectric layer is disposed on the III-V substrate, and the gate is disposed on the gate dielectric layer, and the gate dielectric layer is praseodymium oxide (PrxOy), which has a high dielectric constant and a high band gap. By using the praseodymium oxide (Pr6O11) as the material of the gate dielectric layer in the present invention, the leakage current could be inhibited, and the equivalent oxide thickness (EOT) of the device with the III-V substrate could be further lowered.Type: ApplicationFiled: December 13, 2010Publication date: April 5, 2012Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Edward-Yi Chang, Yueh-Chin Lin
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Patent number: 8093627Abstract: This nitride semiconductor device comprises: an n-type first layer made of a group III nitride semiconductor; a p-type second layer made of a group III nitride semiconductor layer provided on the first layer; and an n-type third layer made of a group III nitride semiconductor with a p-type impurity content of not more than 1×1018 cm?3 provided on the second layer.Type: GrantFiled: December 26, 2008Date of Patent: January 10, 2012Assignee: Rohm Co., Ltd.Inventors: Hirotaka Otake, Kentaro Chikamatsu
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Patent number: 8080484Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.Type: GrantFiled: March 9, 2009Date of Patent: December 20, 2011Assignee: Showa Denko K.K.Inventors: Yasunori Yokoyama, Hisayuki Miki
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Patent number: 7956361Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.Type: GrantFiled: July 9, 2010Date of Patent: June 7, 2011Assignee: Canon Kabushiki KaishaInventor: Tatsuya Iwasaki
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Patent number: 7935582Abstract: An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled.Type: GrantFiled: July 9, 2010Date of Patent: May 3, 2011Assignee: Canon Kabushiki KaishaInventor: Tatsuya Iwasaki
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Publication number: 20110018040Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.Type: ApplicationFiled: July 27, 2009Publication date: January 27, 2011Inventors: R. Peter Smith, Scott T. Sheppard
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Publication number: 20110006345Abstract: A field effect transistor according to the present invention includes A field effect transistor, comprising: a nitride-based semiconductor multilayer structure, at least including, a drift layer formed of n-type or i-type AlxGa1-xN (0?X?0.Type: ApplicationFiled: January 21, 2009Publication date: January 13, 2011Applicant: NEC CORPORATIONInventors: Kazuki Ota, Yasuhiro Okamoto
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Patent number: 7843006Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.Type: GrantFiled: February 1, 2007Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Rainald Sander, Markus Zundel
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Publication number: 20100285649Abstract: An apparatus includes a field-effect transistor (FET). The FET includes a region of first semiconductor and a layer of second semiconductor that is located on the region of the first semiconductor. The layer and region form a semiconductor heterostructure. The FET also includes source and drain electrodes that are located on one of the region and the layer and a gate electrode located to control a conductivity of a channel portion of the semiconductor heterostructure. The channel portion is located between the source and drain electrodes. The gate electrode is located vertically over the channel portion and portions of the source and drain electrodes.Type: ApplicationFiled: June 11, 2010Publication date: November 11, 2010Inventor: Robert L. Willett
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Patent number: 7811937Abstract: The present invention relates to an apparatus and a method of fabricating a thin film transistor array substrate. The apparatus includes a dip strip component for stripping a photo-resist pattern and a thin film formed on a substrate by using a stripper; a removing part for removing residual photo-resist and thin film from the substrate; and a jet strip component for jetting the stripper to remove residual particles of photo-resist and thin film left on the substrate. The method of fabricating includes dipping a substrate in a stripper, wherein the substrate has a photo-resist pattern and a thin film, the thin film being formed on an entire surface of the substrate so as to cover the photo-resist pattern; removing residual photo-resist and thin film using the stripper; and removing particles of residual photo-resist and thin film left on the substrate.Type: GrantFiled: October 12, 2004Date of Patent: October 12, 2010Assignee: LG Display Co., Ltd.Inventors: Ob Nam Kwon, Heung Lyul Cho
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Publication number: 20100252863Abstract: A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes.Type: ApplicationFiled: March 3, 2010Publication date: October 7, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hisao KAWASAKI
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Patent number: 7777227Abstract: A non-volatile semiconductor storage device includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed of polysilicon on the first insulating layer, a pair of conductor regions formed on the first insulating layer to pass through the semiconductor layer and to sandwich a part of the semiconductor layer, and formed of a metal or a silicide, a tunnel layer formed on the part of the semiconductor layer sandwiched between the pair of conductor regions, a charge storage layer formed on the tunnel layer, a second insulating layer formed on the charge storage layer, and a control gate formed on the second insulating layer.Type: GrantFiled: August 7, 2007Date of Patent: August 17, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Fumitaka Arai
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Publication number: 20100127307Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.Type: ApplicationFiled: December 16, 2009Publication date: May 27, 2010Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
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Publication number: 20100127275Abstract: A GaN-based field effect transistor 101 comprises: a substrate 101; a channel layer 104 comprised of p-type GaN-based semiconductor material formed on the substrate 101; an electron supplying layer 106 formed on said channel layer 104 and comprised of GaN-based semiconductor material which has band gap energy greater than that of said channel layer 104; a gate insulating film 111 formed on a surface of said channel layer which was exposed after a part of said electron supplying layer was removed; a gate electrode 112 formed on said gate insulating film; a source electrode 109 and a drain electrode 110 formed so that said gate electrode 112 positions in between them; and a second insulating film 113 formed on said electron supplying layer, which is a different insulating film from said gate insulating film 111 and has electron collapse decreasing effect.Type: ApplicationFiled: November 25, 2009Publication date: May 27, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nomura Takehiko, Sato Yoshihiro, Kambayashi Hiroshi, Kaya Shusuke, Iwami Masayuki, Kato Sadahiro
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Publication number: 20100123205Abstract: A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 ? to 400 ? on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.Type: ApplicationFiled: November 17, 2008Publication date: May 20, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joel P. de Souza, Keith E. Fogel, Edward W. Kiewra, Steven J. Koester, Christopher C. Parks, Devendra K. Sadana, Shahab Siddiqui
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Patent number: 7696061Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.Type: GrantFiled: September 26, 2007Date of Patent: April 13, 2010Assignee: NEC Electronics CorporationInventor: Hitoshi Ninomiya