Abstract: A method of fabricating a Light Emitting Diode with improved light extraction efficiency, comprising depositing a plurality of Zinc Oxide (ZnO) nanorods on one or more surfaces of a III-Nitride based LED, by growing the ZnO nanorods from an aqueous solution, wherein the surfaces are different from c-plane surfaces of III-Nitride and transmit light generated by the LED.

Abstract: Provided are a composition for an oxide semiconductor, a preparation method of the composition, a method for forming an oxide semiconductor thin film using the composition, and a method for forming an electronic device using the composition. The composition for an oxide semiconductor includes a compound for an oxide thin film and a stabilizer for adjusting conductivity of the oxide thin film. The stabilizer is included with the mole number of two to twelve times larger than the total mole number of the compound.

Abstract: The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate.

Abstract: Disclosed is a solution composition for forming a thin film transistor including a zinc-containing compound, an indium-containing compound, and a compound including at least one metal or metalloid selected from the group consisting of hafnium (Hf), magnesium (Mg), tantalum (Ta), cerium (Ce), lanthanum (La), silicon (Si), germanium (Ge), vanadium (V), niobium (Nb), and yttrium (Y). A method of forming a thin film by using the solution composition, and a method of manufacturing thin film transistor including the thin film are also disclosed.

Abstract: A display substrate includes a gate wire formed on an insulating substrate, a semiconductor pattern formed on the gate wire and containing a metal oxynitride compound, and a data wire formed on the semiconductor pattern to cross the gate wire. The semiconductor pattern has a carrier number density ranging from 1016/cm3 to 1019/cm3.

Abstract: Methods, materials, apparatus and systems are described for implementing high-performance arsenic (As)-doped indium oxide (In2O3) nanowires for transparent electronics, including their implementation in transparent thin-film transistors (TTFTs) and transparent active-matrix organic light-emitting diodes (AMOLED) displays. In one implementation, a method of fabricating n-type dopant-doped metal oxide nanowires includes dispersing nanoparticle catalysts on a Si/SiO2 substrate. n-type dopant-doped metal oxide nanowires are grown on the Si/SiO2 substrate using a laser ablation process.

Abstract: An object is to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, impurities such as moisture existing in the gate insulating layer are reduced before formation of the oxide semiconductor film, and then heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. After that, slow cooling is performed in an oxygen atmosphere. Besides impurities such as moisture existing in the gate insulating layer and the oxide semiconductor film, impurities such as moisture existing at interfaces between the oxide semiconductor film and upper and lower films provided in contact therewith are reduced.

Abstract: Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.

Abstract: A method for fabricating a field-effect transistor having a gate electrode, a source electrode, a drain electrode, and an active layer forming a channel region, the active layer having an oxide semiconductor mainly containing magnesium and indium is disclosed. The method includes a deposition step of depositing an oxide film, a patterning step of patterning the oxide film by processes including etching to obtain the active layer, and a heat-treatment step of heat-treating the obtained active layer subsequent to the patterning step.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.

Abstract: A system and associated process for vapor deposition of a thin film layer on a photovoltaic (PV) module substrate is includes establishing a vacuum chamber and introducing the substrates individually into the vacuum chamber. A conveyor system is operably disposed within the vacuum chamber and is configured for conveying the substrates in a serial arrangement through a vapor deposition apparatus within the vacuum chamber at a controlled constant linear speed. A post-heat section is disposed within the vacuum chamber immediately downstream of the vapor deposition apparatus in the conveyance direction of the substrates. The post-heat section is configured to maintain the substrates conveyed from the vapor deposition apparatus in a desired heated temperature profile until the entire substrate has exited the vapor deposition apparatus.

Abstract: A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain.

Abstract: Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for depositing a Cu-rich precursor layer followed by a Cu-poor precursor layer. Methods are described for depositing a Cu-poor precursor layer followed by a Cu-rich precursor layer. Methods are described for depositing a Cu-poor precursor layer followed by a Cu-poor precursor layer. Methods are described for depositing a Cu-rich precursor layer followed by removing excess Cu-chalcogenide using a wet etch, followed by a Cu-poor precursor layer. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer.

Abstract: Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and alternately repeating a first introducing at least a silane-compound gas into the processing chamber and a second introducing at least etching gas a plurality of times to selectively grow an epitaxial film on the silicon surface, wherein the alternate repeating is started with the second introducing prior to the first introducing.

Abstract: A thin film transistor, which has a first passivation layer and a second passivation layer to maintain high reliability while preventing hydrogen from being induced to a semiconductor layer, and a method for fabricating the thin film transistor are provided. The method includes providing a substrate including an insulation substrate, forming a gate electrode on the substrate, forming a gate insulation layer on the substrate and the gate electrode, forming a semiconductor layer on the gate insulation layer, forming source/drain electrodes on the semiconductor layer to expose a portion of a top portion of the semiconductor layer, forming a first passivation layer to cover exposed top portions of the gate insulation layer, the semiconductor layer and the source/drain electrodes, and forming a second passivation layer on the first passivation layer, wherein the forming of the second passivation layer comprises performing deposition at a higher temperature than the forming of the first passivation layer.

Abstract: A method of manufacturing a semiconductor for a transistor that includes forming a precursor layer by coating a surface of an insulation substrate with a precursor solution for an oxide semiconductor, forming an oxide semiconductor by oxidizing a portion of the precursor layer, and removing a remaining precursor layer except for the oxide semiconductor.

Abstract: A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.

Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.

Abstract: An amorphous region with low density is formed in an oxide insulating film containing zirconium. The amount of oxygen released from such an oxide insulating film containing zirconium by heating is large and a temperature at which oxygen is released is higher in the oxide insulating film than in a conventional oxide film (e.g., a silicon oxide film). When the insulating film is formed using a sputtering target containing zirconium in an oxygen atmosphere, the temperature of a surface on which the insulating film is formed may be controlled to be lower than a temperature at which a film to be formed starts to crystallize.

Abstract: A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.

Abstract: A novel method for fabrication of hybrid semiconductor-graphene nanostructures in large scale by floating graphene sheets on the surface of a solution is provided. Using this approach, crystalline ZnO nano/micro-rod bundles on graphene fabricated using chemical vapor deposition were prepared. UV detectors fabricated using the as-prepared hybrid ZnO-graphene nano-structure with graphene being one of the two electrodes show high sensitivity to ultraviolet light, suggesting the graphene remained intact during the ZnO growth. This growth process provides a low-cost and robust scheme for large-scale fabrication of semiconductor nanostructures on graphene and may be applied for synthesis of a variety of hybrid semiconductor-graphene nano-structures demanded for optoelectronic applications including photovoltaics, photodetection, and photocatalysis.

Abstract: Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

Abstract: In one or more embodiments, methods of fabricating current-confining stack structures in a phase-change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed.

Abstract: The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (11?)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.

Abstract: The present invention relates to a device for processing substrates in a processing system with at least one process tool disposed in at least one process area, which tool has two substrate levels disposed opposite each other in the process area, which are aligned at least approximately vertical, wherein the device is adapted to process at least two substrates at the same time in the process area by means of the process tool, wherein the substrates can be disposed in the substrate levels such that coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates. It further relates to a method for processing coated substrates in a processing system, wherein the substrates have coatings and the substrates are each disposed opposite each other such that the coatings of the substrates face each other and, at least during processing, a quasi-closed process space is formed between the substrates.

Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.

Abstract: The present invention relates to a carbon nanotube-invaded metal oxide composite film used as an N-type metal oxide conductive film of an organic solar cell, a manufacturing method thereof, and the organic solar cell with an improved photoelectric conversion efficiency and improved durability using the same, and more specifically, to a metal oxide-carbon nanotube composite film, a manufacturing method thereof, and an organic solar cell with an improved photoelectric conversion efficiency and improved durability using the same, characterized in that a single-wall carbon nanotube which has been surface-treated by a metal oxide is uniformly dispersed and is combined with the metal oxide.

Abstract: An organic light emitting display device and a method for manufacturing the same. The organic light emitting display device includes: an insulating layer formed on a substrate; a resistance layer of oxide semiconductor formed on the insulating layer; a wiring layer connected to both side portions of the resistance layer; an organic layer formed on the upper portion including the resistance layer and the wiring layer; and a capping layer formed on the organic layer to be overlapped with the resistance layer.

Abstract: Reading margin is improved in a MTJ designed for MRAM applications by employing a pinned layer with an AP2/Ru/AP1 configuration wherein the AP1 layer is a CoFeB/CoFe composite and by forming a MgO tunnel barrier adjacent to the CoFe AP1 layer by a sequence that involves depositing and oxidizing a first Mg layer with a radical oxidation (ROX) process, depositing and oxidizing a second Mg layer with a ROX method, and depositing a third Mg layer on the oxidized second Mg layer. The third Mg layer becomes oxidized during a subsequent anneal. MTJ performance may be further improved by selecting a composite free layer having a Fe/NiFeHf or CoFe/Fe/NiFeHf configuration where the NiFeHf layer adjoins a capping layer in a bottom spin valve configuration. As a result, read margin is optimized simultaneously with improved MR ratio, a reduction in bit line switching current, and a lower number of shorted bits.

Abstract: Provided is a method of manufacturing a sensor structure, where vertically-well-aligned nanotubes are formed and the sensor structure having an excellent performance can be manufactured at the room temperature at low cost by using the nanotubes. The method of manufacturing a sensor structure includes: (a) forming a lower electrode on a substrate; (b) forming an organic template having a pore structure on the lower electrode; (c) forming a metal oxide thin film in the organic template; (d) forming a metal oxide nanotube structure, in which nanotubes are vertically aligned and upper portions thereof are connected to each other, by removing the organic template through a dry etching method; and (e) forming an upper electrode on the upper portions of the nanotubes.

Abstract: A ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3/ZnO nanowire, a nanogenerator including a ZnSnO3/ZnO nanowire, a method of forming a ZnSnO3 nanowire, and a nanogenerator including a ZnSnO3 nanowire are provided. The ZnSnO3/ZnO nanowire includes a core and a shell that surrounds the core, wherein the core includes ZnSnO3 and the shell includes ZnO.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel area of the substrate, and a first metal layer on the dielectric layer. Hydrogen ions are implanted with a plasma-immersion ion implantation process in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The hydrogen ion implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.

Abstract: In a method for growing a nanowire array, a photoresist layer is placed onto a nanowire growth layer configured for growing nanowires therefrom. The photoresist layer is exposed to a coherent light interference pattern that includes periodically alternately spaced dark bands and light bands along a first orientation. The photoresist layer exposed to the coherent light interference pattern along a second orientation, transverse to the first orientation. The photoresist layer developed so as to remove photoresist from areas corresponding to areas of intersection of the dark bands of the interference pattern along the first orientation and the dark bands of the interference pattern along the second orientation, thereby leaving an ordered array of holes passing through the photoresist layer. The photoresist layer and the nanowire growth layer are placed into a nanowire growth environment, thereby growing nanowires from the nanowire growth layer through the array of holes.

Abstract: The invention relates to a printable precursor comprising an organometallic zinc complex which contains at least one ligand from the class of the oximates and is free from alkali metals and alkaline-earth metals, for electronic components and to a preparation process. The invention furthermore relates to corresponding printed electronic components, preferably field-effect transistors.

Abstract: To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film.

Abstract: Disclosed are a nanostructure array substrate, a method for fabricating the same, and a dye-sensitized solar cell by using the same. The nanostructure array substrate includes a plurality of metal oxide nanostructures vertically aligned on the substrate while being separated from each other. The metal oxide nanostructures include nanorods having a ZnO core/TiO2 shell structure or TiO2 nanotubes. The method includes the steps of forming ZnO nanorods vertically aligned from a seed layer formed on a substrate; and coating a TiO2 sol on the ZnO nanorods and sintering the ZnO nanorods to form nanorods having a ZnO core/TiO2 shell structure. The transparency and flexibility of the substrate are ensured. The photoelectric conversion efficiency of the solar cell is improved if the nanostructure array substrate is employed in the photo electrode of the dye-sensitized solar cell.

Abstract: Si(1-v-w-x)CwAlxNv crystals in a mixed crystal state are formed. A method for manufacturing an easily processable Si(1-v-w-x)CwAlxNv substrate, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer are provided. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer 12 (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate 11 by a pulsed laser deposition method.

Abstract: An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.

Abstract: In an oxide semiconductor film formed over an insulating surface, an amorphous region remains in the vicinity of the interface with the base, which is thought to cause a variation in the characteristics of a transistor and the like. A base surface or film touching the oxide semiconductor film is formed of a material having a melting point higher than that of a material used for the oxide semiconductor film. Accordingly, a crystalline region is allowed to exist in the vicinity of the interface with the base surface or film touching the oxide semiconductor film. An insulating metal oxide is used for the base surface or film touching the oxide semiconductor film. The metal oxide used here is an aluminum oxide, gallium oxide, or the like that is a material belonging to the same group as the material of the oxide semiconductor film.

Abstract: A semiconductor device includes a gate electrode, a gate insulating film provided so as to cover one surface of the gate electrode, an oxide semiconductor provided so as to overlap the gate insulating film, and a source electrode and a drain electrode, which are provided so as to overlap the oxide semiconductor. The semiconductor device also includes an oxygen-atom-containing film provided between the gate insulating film, and, the source electrode and the drain electrode, so as to be held in contact with the oxide semiconductor.

Abstract: A method of making an electronic device comprising a double bank well-defining structure, which method comprises: providing an electronic substrate; depositing a first insulating material on the substrate to form a first insulating layer; depositing a second insulating material on the first insulating layer to form a second insulating layer; removing a portion of the second insulating layer to expose a portion of the first insulating layer and form a second well-defining bank; depositing a resist on the second insulating layer and on a portion of the exposed first insulating layer; removing the portion of the first insulating layer not covered by the resist, to expose a portion of the electronic substrate and form a first well-defining bank within the second well-defining bank; and removing the resist. The method can provide devices with reduced leakage currents.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: A method of fabricating a gallium nitride (GaN) substrate provides a GaN thick film without causing bending and cracks which may occur in a growing process. To this end, a nitride embedding layer having a plurality of voids therein is embedded between a GaN layer and a base substrate. The method includes preparing a base substrate, growing, on the base substrate, the nitride embedding layer having a plurality of indium-rich parts at a first temperature, and growing a GaN layer on the nitride embedding layer at a second temperature higher than the first temperature so as to metallize the indium-rich part to form a plurality of voids in the nitride embedding layer.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession.

Abstract: An oxide semiconductor device includes a gate electrode on a substrate, a gate insulation layer on the substrate, the gate insulation layer having a recess structure over the gate electrode, a source electrode on a first portion of the gate insulation layer, a drain electrode on a second portion of the gate insulation layer, and an active pattern on the source electrode and the drain electrode, the active pattern filling the recess structure.

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.

Abstract: The present invention is directed to a novel synthetic method for producing nanoscale heterostructures, and particularly nanoscale heterostructure particles, rods and sheets, that comprise a metal core and a monocrystalline semiconductor shell with substantial lattice mismatches between them. More specifically, the invention concerns the use of controlled soft acid-base coordination reactions between molecular complexes and colloidal nanostructures to drive the nanoscale monocrystalline growth of the semiconductor shell with a lattice structure incommensurate with that of the core. The invention also relates to more complex hybrid core-shell structures that exhibit azimuthal and radial nano-tailoring of structures. The invention is additionally directed to the use of such compositions in semiconductor devices.