Abstract: To suppress desorption of hydrogen ions with which a single crystal semiconductor substrate is irradiated. A method for manufacturing an SOI substrate includes the following steps: irradiating a semiconductor substrate with carbon ions; irradiating the semiconductor substrate with a hydrogen ion after the irradiation with the carbon ion so as to form an embrittled region in the semiconductor substrate; disposing a surface of the semiconductor substrate and a surface of a base substrate to face each other and to be in contact with each other so that the semiconductor substrate and the base substrate are bonded; and heating the semiconductor substrate and the base substrate which are bonded to each other and separating the semiconductor substrate along the embrittled region so that a semiconductor layer is formed over the base substrate.

Abstract: The present invention provides a temporary carrier bonding and detaching process. A first surface of a semiconductor wafer is mounted on a first carrier by a first adhesive layer, and a first isolation coating disposed between the first adhesive layer and the first carrier. Then, a second carrier is mounted on the second surface of the semiconductor wafer. The first carrier is detached. Then, the first surface of the semiconductor wafer is mounted on a film frame. The second carrier is detached. The method of the present invention utilizes the second carrier to support and protect the semiconductor wafer, after which the first carrier is detached. Therefore, the semiconductor wafer will not be damaged or broken, thereby improving the yield rate of the semiconductor process. Furthermore, the simplicity of the detaching method for the first carrier allows for improvement in efficiency of the semiconductor process.

Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract: The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.

Abstract: Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.

Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.

Abstract: After a single crystal semiconductor layer provided over a base substrate by attaching is irradiated with a laser beam, characteristics thereof are improved by first heat treatment, and after adding an impurity element imparting conductivity to the single crystal semiconductor layer, second heat treatment is performed at lower temperature than that of the first heat treatment.

Abstract: The present invention relates to a process for preparing semiconductor-on-insulator type structures that include a semiconductor layer of a donor substrate, an insulator layer and a receiver substrate. The process includes bonding of the donor substrate onto the receiver substrate, with at least one of the substrates being coated with an insulator layer, and forming at the bonding interface a so-called trapping interface of electrically active traps suitable for retaining charge carriers. The invention also relates to a semiconductor-on-insulator type structure that includes such a trapping interface.

Abstract: To provide an input device including a display screen which has an image display function and a text information input function by using a display portion in which a pixel includes an optical sensor. An optical sensor is provided in each pixel of the display portion in order to detect position information. A transistor of a pixel circuit in the display portion and the optical sensor are formed using a single crystal semiconductor layer. By using the single crystal semiconductor layer, there is no variation in characteristics among pixels, and position detection with high accuracy is realized. Moreover, the display portion is formed using a substrate which is a light-transmitting substrate such as a glass substrate provided with a single crystal semiconductor layer separated from a single crystal semiconductor substrate.

Abstract: A method for preparing a thin layer of GaN from a starting substrate in which at least one thick surface area extending along a free face of the starting substrate includes GaN, where the method includes bombarding the free face of the substrate with helium and hydrogen atoms, the helium being implanted first into the thickness of the thick surface area and the hydrogen being implanted thereafter, and where the helium and hydrogen doses each vary between 1.1017 atoms/cm2 and 4.1017 atoms/cm2. The starting substrate is subjected to a rupture process in order to induce the separation, relative to a residue of the starting substrate, of the entire portion of the thick area located between the free face and the helium and hydrogen implantation depth. The helium is advantageously implanted in a dose at least equal to that of hydrogen, and can also be implanted alone.

Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.

Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.

Abstract: In order to keep the crystallinity of the semiconductor thin film layer high, a temperature of a semiconductor substrate during hydrogen ion addition treatment is suppressed to lower than or equal to 200° C. In addition, the semiconductor substrate is subjected to plasma treatment while the semiconductor substrate is kept at a temperature of higher than or equal to 100° C. and lower than or equal to 400° C. after the hydrogen ion addition treatment, whereby Si—H bonds which have low contribution to separation of the semiconductor thin film layer can be reduced while Si—H bonds which have high contribution to separation of the semiconductor thin film layer, which are generated by the hydrogen ion addition treatment, are kept.

Abstract: A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate; heat-treating the laminated substrate and diffusing outwardly the oxide film.

Abstract: In the method for manufacturing a semiconductor device of the invention, a bonding layer is formed over a substrate, an insulating film and a storage capacitor portion lower electrode are formed over the bonding layer, a single crystal silicon layer is formed over the insulating film, a storage capacitor portion insulating film is formed over the storage capacitor portion lower electrode, a wiring is formed over the storage capacitor portion insulating film, a channel forming region and a low concentration impurity region are formed over the single crystal silicon layer, and a gate insulating film and a gate electrode are formed over the single crystal silicon layer. The storage capacitor portion insulating film is formed by depositing a YSZ film with a single crystal silicon layer used as a base film, whereby the permittivity increases and thus the leakage current from the storage capacitor portion is suppressed.

Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Abstract: An optical device layer (ODL) in an optical device wafer is transferred to a transfer substrate. The ODL is formed on the front side of an epitaxy substrate through a buffer layer. The ODL is partitioned by a plurality of crossing streets to define regions where a plurality of optical devices are formed. The transfer substrate is bonded to the front side of the ODL, and the epitaxy substrate is cut along crossing streets into a plurality of blocks. A laser beam is applied to the epitaxy substrate from the back side of the epitaxy substrate to the unit of the optical device wafer and the transfer substrate in the condition where the focal point of the laser beam is set in the buffer layer, thereby decomposing the buffer layer. The epitaxy substrate divided into the plurality of blocks is peeled off from the ODL.

Abstract: A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach the detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues.

Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).

Abstract: There is provided an SOS substrate with reduced stress. The SOS substrate is a silicon-on-sapphire (SOS) substrate comprising a sapphire substrate and a monocrystalline silicon film on or above the sapphire substrate. The stress of the silicon film of the SOS substrate as measured by a Raman shift method is 2.5×108 Pa or less across an entire in-plane area of the SOS substrate.

Abstract: An SOI substrate is manufactured by forming an embrittled layer in a bond substrate by increasing the dose of hydrogen ions in the formation of the embrittled layer to a value more than the dose of hydrogen ions of the lower limit for separation of the bond substrate, separating the bond substrate attached to the base substrate, forming an SOI substrate in which a single crystal semiconductor film is formed over the base substrate, and irradiating a surface of the single crystal semiconductor film with laser light.

Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength ? comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.

Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.

Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.

Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.

Abstract: A method for producing a bonded substrate having a Si1-xGex (0<x?1) film in which a larger than ever biaxial strain has been introduced. Specifically, the method involves at least the steps of: providing a donor wafer and a handle wafer having a thermal expansion coefficient lower than the donor wafer, implanting ions of any one or both of hydrogen and a noble gas into the donor wafer to form an ion-implanted layer, performing a plasma activation treatment on at least one of bonding surfaces of the donor wafer and the handle wafer, bonding the donor wafer to the handle wafer, splitting the donor wafer through application of a mechanical impact to the ion-implanted layer, performing a surface treatment on a split surface of the donor wafer, and epitaxially growing a Si1-xGex (0<x?1) film on the split surface to thus form a strained Si1-xGex (0<x?1) film on the bonded wafers.

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.

Abstract: In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer.

Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.

Abstract: A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate.

Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract: Provided is a semiconductor device in which a short margin between a storage contact plug and a bit line contact plug may be increased. The device includes a substrate including isolation regions and active regions defined by the isolation regions, gates disposed in the substrate and configured to intersect the active regions and define source regions and drain regions in the active regions, an interlayer insulating layer disposed on the substrate, bit line contact plugs configured to penetrate the interlayer insulating layer and contact the drain regions, and first bit line structures and second bit line structures disposed on the interlayer insulating layer. The first bit line structures include first bit line conductive patterns and first bit line spacers covering sidewalls of the first bit line conductive patterns.

Abstract: A method of fabricating an electronic device includes providing a silicon carbide or diamond-like carbon donor body and implanting ions into a first surface of the donor body to define a cleave plane. After implanting, an epitaxial layer is formed on the first surface, and a temporary carrier is coupled to the epitaxial layer. A lamina is cleaved from the donor body at the cleave plane, and the temporary carrier is removed from the lamina. In some embodiments a light emitting diode or a high electron mobility transistor is fabricated from the lamina and epitaxial layer.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

Abstract: A method for producing a structure having an ultra thin buried oxide (UTBOX) layer by assembling a donor substrate with a receiver substrate wherein at least one of the substrates includes an insulating layer having a thickness of less than 50 nm that faces the other substrate, conducting a first heat treatment for reinforcing the assembly between the two substrates at temperature below 400° C., and conducting a second heat treatment at temperature above 900° C., wherein the exposure time between 400° C. and 900° C. between the heat treatments is less than 1 minute and advantageously less than 30 seconds.

Abstract: The invention relates to finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two semiconducting material layers. The method successively comprises routing the annular periphery of the substrate so as to obtain a routed substrate, and encapsulating the routed substrate so as to cover the routed side edge of the buried insulator layer by means of a semiconducting material.

Abstract: According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer.

Abstract: Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured.

Abstract: A method for transferring a monocrystalline semiconductor layer onto a support substrate by implanting species in a donor substrate; bonding the donor substrate to the support substrate; and fracturing the donor substrate to transfer the layer onto the support substrate; wherein a portion of the monocrystalline layer to be transferred is rendered amorphous, without disorganizing the crystal lattice of a second portion of the layer, with the portions being, respectively, a surface portion and a buried portion of the monocrystalline layer; and wherein the amorphous portion is recrystallized at a temperature below 500° C., with the crystal lattice of the second portion serving as a seed for recrystallization.

Abstract: To provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like is used. The semiconductor layer is transferred to a supporting substrate by the steps of irradiating a semiconductor wafer with ions from one surface to form a damaged layer; forming an insulating layer over one surface of the semiconductor wafer; attaching one surface of the supporting substrate to the insulating layer formed over the semiconductor wafer and performing heat treatment to bond the supporting substrate to the semiconductor wafer; and performing separation at the damaged layer into the semiconductor wafer and the supporting substrate. The damaged layer remaining partially over the semiconductor layer is removed by wet etching and a surface of the semiconductor layer is irradiated with a laser beam.

Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.

Abstract: A hexagonal boron nitride thin film is grown on a metal surface of a growth substrate and then annealed. The hexagonal boron nitride thin film is coated with a protective support layer and released from the metal surface. The boron nitride thin film together with the protective support layer can then be transferred to any of a variety of arbitrary substrates.

Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.

Abstract: A semiconductor device may have a thickness, such that the semiconductor devices are not flexible, and may be bonded and electrically coupled on a flexible substrate. After this bonding, the semiconductor device may be thinned so as to be rendered flexible.

Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.

Abstract: To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer 7 by forming a silicon film layer on a surface 4 of an insulating substrate 3 comprising the steps in the following order of: applying a surface activation treatment to both a surface 2 of a silicon wafer 1 or a silicon wafer 1 to which an oxide film is layered and a surface 4 of the insulating substrate 3 followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer 5 at a temperature of 200° C. to 350° C., and thinning the silicon wafer 1 by a combination of grinding, etching and polishing to form a silicon film layer.

Abstract: A porous Si layer is formed on a single-crystal Si substrate, and then a p+-type Si layer, p-type Si layer and n+-type Si layer which all make up a solar cell layer. After a protective film is made on the n+-type Si layer, the rear surface of the single-crystal Si substrate is bonded to a tool, and another tool is bonded to the front surface of the protective film. Theo, the tools are pulled in opposite directions to mechanically rupture the porous Si layer and to separate the solar cell layer from the single-crystal substrate. The solar cell layer is subsequently sandwiched between two plastic substrates to make a flexible thin-film solar cell.