Abstract: A method for efficiently removing hardened polymer residues generated in the process of forming metal lines. The method includes forming a metal layer over a lower film, forming a sacrificial protective film over the metal layer, forming a photosensitive pattern over the sacrificial protective film, forming a metal line by selectively etching the sacrificial protective film and the metal layer using the photosensitive pattern as a mask such that a residual sacrificial protective film is formed over the metal line, and then removing the residual sacrificial protective film from the metal line.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit. Apparatus and systems having such structures and methods of forming these structures for apparatus and systems are disclosed.

Abstract: A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.

Abstract: A direct patterning method for manufacturing a metal layer of a semiconductor device is provided. The claimed method reduces the materials and hours required by prior methods such as the thin film depositing method for a substrate, and the photolithographic method for manufacturing a transistor. The preferred embodiment of the present invention comprises a step of defining the pattern of the seeder material and a step of selectively thin film deposition. The direct patterned technology for the seeder and a chemical bath deposition (CBD) are utilized to provide the thin film growing method with non-vacuum and selective deposition. The object of the invention is applied to produce the wire or electrode, within the semiconductor device, or to deposit and manufacture the thin film in the large-area transistor array or a reflective layer.

Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.

Abstract: Electro-mechanical switches and memory cells using vertically-oriented nanofabric articles and methods of making the same. Under one aspect, a nanotube device includes a substantially horizontal substrate having a vertically oriented feature; and a nanotube film substantially conforming to a horizontal feature of the substrate and also to at least the vertically oriented feature. Under another aspect, an electromechanical device includes a structure having a major horizontal surface and a channel formed therein, the channel having first and second wall electrodes defining at least a portion of first and second vertical walls of the channel; first and second nanotube articles vertically suspended in the channel and in spaced relation to a corresponding first and second wall electrode, and electromechanically deflectable in a horizontal direction toward or away from the corresponding first and second wall electrode in response to electrical stimulation.

Abstract: An article includes a substrate and a metal layer adhered to a surface of the substrate so as to form an interface. The interface comprises an atomic concentration of carbon that is about 10% or less and of oxygen that is about 10% or less as determined by x-ray photoelectron spectroscopy.

Abstract: A device for optical communication includes an organic optical waveguide having a core part and a cladding part. The core part and the cladding part comprise a polymer material, and the cladding part includes particles.

Abstract: A method for forming a three-dimensional structure comprises: a first step of dropping a liquid material containing a structure-forming material and a solvent onto a structure forming surface; and a second step of drying at least a part of the solvent in the dropped liquid material to form a deposit layer on the structure forming surface, wherein the first step and the second step are repeated while a dropping position of the liquid material is shifted such that a next droplet of the liquid material is dropped onto the deposit layer formed of the previously-dropped liquid material to repeatedly accumulate the deposit layers on the structure forming surface, thereby forming a three-dimensional structure having at least one inclination portion inclined with respect to the structure forming surface.

Abstract: A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved.

Abstract: The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

Abstract: A method for production of semiconductor devices which includes the steps of forming, on an interlayer insulating film formed on a substrate, a copper-containing conductive layer in such a way that its surface is exposed, performing heat treatment with a reducing gas composed mainly of hydrogen on the surface of the conductive layer, performing plasma treatment with a reducing gas on the surface of the conductive layer, thereby permitting the surface of the conductive layer to be reduced and the hydrogen adsorbed by the heat treatment to be released, and forming an oxidation resistance film that covers the surface of the conductive layer such that the surface of the conductive layer is not exposed to an oxygen-containing atmospheric gas after the plasma treatment.

Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract: A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-holes, sequentially forming at least two metal layers on the interlayer dielectric layer formed with the plugs, the metal layers having a difference in the size of metal grains of each metal layer, etching an uppermost first metal layer of the at least two metal layers using a photoresist pattern formed on the first metal layer as an etching mask using a first etching gas, and etching the partially etched first metal layer using a second etching gas.

Abstract: The present invention is to provide a “fabricating method for quantum dot active layer of LED by nano-lithography” for fabricating out a new active layer of LED of nano quantum dot structure in more miniature manner than that of the current fabricating facilities to have high quality LED with features in longer light wavelength, brighter luminance and lower forward bias voltage by directly using the current fabricating facilities without any alteration or redesign of the precision.

Abstract: A method of forming an interconnect structure of an integrated circuit includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; and forming a copper alloy seed layer in the opening. The copper alloy seed layer physically contacts the dielectric layer. The copper alloy seed layer includes copper and an alloying material. The method further includes filling a metallic material in the opening and over the copper alloy seed layer; performing a planarization to remove excess metallic material over the dielectric layer; and performing a thermal anneal to cause the alloying material in the copper alloy seed layer to be segregated from copper.

Abstract: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.

Abstract: A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecting a portion of the dielectric layer at an edge of the via hole by selectively etching the dielectric layer to a first depth, and forming a trench by selectively etching the dielectric layer to a second depth, wherein the trench is overlapped with the via hole to form a dual damascene pattern.

Abstract: A method of selective formation of suicide on a semiconductor wafer, wherein the metal layer (12) is deposited over the entire wafer prior to application of the SiProt mask (10, 16, 22) such that any etching of the mask (10, 16, 22) does not cause any surface deterioration of the silicon wafer.

Abstract: Methods of depositing thin seed layers that improve continuity of the seed layer as well as adhesion to the barrier layer are provided. According to various embodiments, the methods involve performing an etchback operation in the seed deposition chamber prior to depositing the seed layer. The etch step removes barrier layer overhang and/or oxide that has formed on the barrier layer. It some embodiments, a small deposition flux of seed atoms accompanies the sputter etch flux of argon ions, embedding metal atoms into the barrier layer. The embedded metal atoms create nucleation sites for subsequent seed layer deposition, thereby promoting continuous seed layer film growth, film stability and improved seed layer-barrier layer adhesion.

Abstract: A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region.

Abstract: A method of manufacturing a semiconductor memory apparatus includes fabricating a cell array to reduce parasite capacitance generated between a bit line and a gate pattern. The method may include determining a plug region by a storage-node plug contact mask and a bit line plug mask. The method may further include: forming a gate pattern of a cell transistor and depositing an insulation layer over a structure including the gate pattern; and forming a hard mask layer over the insulation layer.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: In order to achieve low cost of manufacture of a display device by reducing the use of primary material used in a manufacturing process of a display device and saving labor taken for a vacuum process, according to the invention, liquid droplets containing conductive particles are ejected on a film being processed by using a first liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices, thereby a conductive film is formed. After that, a resist pattern is locally formed on the conductive film by using a second liquid droplet ejecting apparatus having a liquid droplet ejecting head provided with a plurality of liquid droplet ejecting orifices. The conductive film is etched with the resist pattern as a mask to form a wiring.

Abstract: A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated circuitry includes forming a step wall over a semiconductor substrate. Catalytic material is provided proximate the step wall. An elevationally outer surface of the catalytic material is masked with a masking material. The catalytic material and the masking material are patterned to form an exposed end sidewall of the catalytic material proximate the step wall, with remaining of the elevationally outer surface of the catalytic material being masked. A carbon nanotube is grown from the exposed end sidewall of the catalytic material along the step wall generally parallel to the semiconductor substrate. The carbon nanotube is incorporated into a circuit component of an integrated circuit.

Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.

Abstract: An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.

Abstract: The present invention provides a method for manufacturing a thin film transistor (TFT) array panel by forming a gate line having a gate electrode on an insulating substrate; sequentially depositing a gate insulating layer and a semiconductor layer on the gate line; forming a drain electrode and a data line having a source electrode on the gate insulating and semiconductor layers; and forming a pixel electrode connected to the drain electrode. These elements can be formed by photo-etching using an etchant containing 65 wt % to 75 wt % of phosphoric acid, 0.5 wt % to 15 wt % of nitric acid, 2 wt % to 15 wt % of acetic acid, 0.1 wt % to 8.0 wt % of a potassium compound, and deionized water. Each element of the TFT array panel can be patterned with the etchant of the invention under similar conditions, which simplifies a manufacturing process and saves costs and results in TFT elements having a good profile.

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.

Abstract: A CMOS image sensor may include at least one of: a semiconductor substrate over which a photodiode and transistors are formed; passivation layers formed over a semiconductor substrate; and color PRs buried in trenches formed in the passivation layers and formed to be higher than the trenches.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.

Abstract: A patterning method in a semiconductor manufacturing process includes the following steps. A base is provided. A target layer and a lining layer are sequentially formed on the surface of the base. The lining layer is patterned to form a plurality of rectangular blocks. A sidewall spacer material layer is formed on the rectangular blocks and the target layer. Part of the sidewall spacer material layer is removed to form a sidewall spacer on the side wall of each of the plurality of rectangular blocks. The plurality of rectangular blocks is removed, and the sidewall spacer is used as a hard sheltering mask to etch and remove part of the target layer. The overlay accuracy is improved and the dimension of the electronic elements can be reduced so that a lot of two-dimension structures can be manufactured on the wafer substrate.

Abstract: A system and method is disclosed for reducing etch sequencing induced downstream dielectric defects produced in a SOG planarization process used in high volume semiconductor manufacturing. Three factors have been identified as causes of the defects. The three factors are: (1) phosphorus-doping in the base dielectric, and (2) using for SOG etchback an etch tool that was last used for a bond pad etch process, and (3) residual metal contaminants in the etch chamber used for the SOG etchback. Elimination of any one of these three factors eliminates the defects.

Abstract: In a method of forming carbon nanotubes (CNTs) and a method of manufacturing a field emission display (FED) device using the CNTs, the method includes preparing a substrate on which a silicon layer is formed, sequentially forming a buffer layer and a catalyst metal layer on the silicon layer, partly forming metal silicide domains by diffusion between the silicon layer, the buffer layer and the catalyst metal layer by annealing the substrate, and growing CNTs on a surface of the catalyst metal layer.

Abstract: The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing materials and tungsten-containing materials) relative to oxide (such as silicon dioxide) and/or copper. The selective removal can utilize etchant solutions containing hydrofluoric acid and one or more carboxylic acids. The etchant solutions can contain less than 6 weight percent water, and/or can have a dielectric constant below 40.

Abstract: A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.