Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing an underlying semiconductor layer; depositing an insulation layer over the underlying semiconductor layer; forming a first through semiconductor via extending continuously through the insulation layer; forming a second through semiconductor via extending continuously through the insulation layer; etching a portion of the insulation layer to expose a first upper end of the first through semiconductor via above the insulation layer and a second upper end of the second through semiconductor via above the insulation layer; and forming an upper conductive connecting portion laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end by a self-aligned deposition process.

Abstract: The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

Abstract: The present application provides a memory device with an air gap. The memory device includes an active region disposed in a substrate; a word line disposed in the substrate, wherein the word line is intersected with the active region; a contact structure disposed on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure is covered by the first and second conductive layers; a conductive pillar overlapped with and electrically connected to the contact structure; a landing pad covers and electrically connects to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and a dielectric layer laterally surrounding the conductive pillar and the landing pad.

Abstract: A semiconductor structure includes a substrate, a passive device and an active device over the substrate. The active device is formed in the first region of the substrate, and the passive device is formed in the second region of the substrate. The semiconductor structure further includes a passivation layer that covers the top surface of the passive device. The passivation layer has an opening that exposes the active device.

Abstract: A gas sensor device includes: a first electrode; a second electrode; a metal oxide layer that is disposed between the first electrode and the second electrode and is in contact with the first electrode and the second electrode; an interlayer insulating film that covers a part of the first electrode, a part of the second electrode, and a part of the metal oxide layer; and a hydrogen permeable film that allows only hydrogen to permeate, a local region that is in contact with the second electrode is provided inside the metal oxide layer, the local region having a higher oxygen deficiency than an oxygen deficiency of the other region in the metal oxide layer, an opening that exposes a gas contact portion which is a part of a main surface of the second electrode is provided in the interlayer insulating film, and the hydrogen permeable film is provided to cover at least the gas contact portion.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Abstract: Methods for selectively depositing on non-metallic surfaces are disclosed. Some embodiments of the disclosure utilize an unsaturated hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked non-metallic surfaces. Some embodiments of the disclosure relate to methods of forming metallic vias with decreased resistance.

Abstract: An interposer for a processor includes: an electrically insulating material having a first main side and a second main side opposite the first main side; an electrical interface for a processor substrate at the first main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material to a lower voltage. The power device module has at least one contact configured to receive the voltage provided at the second main side of the electrically insulating material. Distribution circuitry embedded in the electrically insulating material is configured to carry the lower voltage provided by the power device module to the first main side of the electrically insulating material.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

Abstract: A semiconductor device includes an interconnect including (i) a first layer, and (ii) a second layer provided on the first layer and including copper. The device also includes a plug provided on the interconnect and including (a) a third layer including titanium and nitrogen, and (b) a fourth layer provided on the third layer and including tungsten. A concentration of chlorine in the third layer is less than or equal to 5.0×1021 atoms/cm3, and a concentration of oxygen at the interface between the third layer and the fourth layer is less than or equal to 5.0×1021 atoms/cm3.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.

Abstract: The present disclosure provides a semiconductor device with a copper-manganese liner and a method for forming the semiconductor device. The semiconductor device includes a first electrode and a second electrode disposed in a first dielectric layer. The semiconductor device also includes a first liner separating the first electrode from the first dielectric layer. The semiconductor device further includes a fuse link disposed in the first dielectric layer. The fuse link is disposed between and electrically connected to the first electrode and the second electrode, and the fuse link and the first liner are made of copper-manganese (CuMn).

Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes forming a conductive structure over a semiconductor substrate, and forming a first inter-layer dielectric (ILD) layer over the conductive structure. The method also includes forming a first spacer and a conductive plug penetrating through the first ILD layer. The conductive plug is electrically connected to the conductive structure, and the first spacer is between the first ILD layer and the conductive plug. The method further includes removing a portion of the first ILD layer to form a gap adjacent to the first spacer, and filling the gap with an energy removable material. In addition, the method includes performing a heat treatment process to transform the energy removable material into a second spacer, wherein the first spacer is separated from the first ILD layer by an air gap after the heat treatment process is performed.

Abstract: A display panel including: a base substrate including first and second surfaces, a display region and a peripheral region; a pixel layer provided on the display region, the pixel layer including a plurality of pixels; a module hole penetrating the display region; a blocking groove in the display region and adjacent to the module hole, the blocking groove being recessed in the base substrate; an encapsulation layer provided on the pixel layer, the encapsulation layer including a first inorganic layer, a second inorganic layer and an organic layer; and a filling member in the blocking groove, the filling member including a same material as the organic layer, wherein the second inorganic layer covers a top surface of the filling member and a top surface of the first inorganic layer adjacent to the top surface of the filling member.

Abstract: A method of manufacturing contacts is provided in the present invention, which include the steps of forming a plurality of mask bars on a substrate, forming a circular mask surrounding each mask bar, wherein the circular masks connect each other and define a plurality of opening patterns collectively with the mask bars, using the mask bars and the circular masks as etch masks to perform an etch process and to transfer the opening patterns and form a plurality recesses in the substrate, and filling up the recesses with metal to form contacts.

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Abstract: An integrated circuit includes a plurality of layers stacked in a first direction, a plurality of unit circuits at least partially overlapping each other in a second direction that is perpendicular to the first direction and configured to operate in parallel with one another, control circuitry configured to generate a control signal to control the plurality of unit circuits, and a multi-layer conducting line configured to transfer the control signal from the control circuitry to the plurality of unit circuits. The multi-layer conducting line may be integrally formed in a wiring layer and a via layer and extends in the second direction. The wiring layer and the via layer may be adjacent to each other.

Abstract: The present disclosure provides a semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer and a method for preparing the same. The semiconductor device structure includes a substrate having a pattern-dense region and a pattern-loose region; a first conductive layer disposed over the substrate; a first dielectric layer disposed over the first conductive layer; a first conductive plug and a second conductive plug disposed in the first dielectric layer; wherein the first conductive plug and the second conductive plug comprises copper (Cu) and are separated from the first dielectric layer by the a first lining layer comprising manganese (Mn); wherein the first conductive plug and the second conductive plug have different aspect ratios.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: A display device is provided including a first conductive line disposed on a substrate. A first insulating layer is disposed on the substrate at least partially covering the first conductive line. The first insulating layer has a contact hole, which exposes the first conductive line, and a groove recessed in a direction towards the substrate. The groove has a depth smaller than a depth of the contact hole. A second conductive line is disposed in the groove on the first insulating layer and is connected to the first conductive line through the contact hole.

Abstract: Embodiments of the present disclosure generally relate to flexible photovoltaic modules that include a multi-layered substrate. In some embodiments, the multi-layered substrate includes one or more layers that are configured to improve the elastic modulus, rigidity, or stiffness of a flexible substrate of a flexible photovoltaic module during a deposition process step at an elevated temperature that is used to form the flexible photovoltaic module. The one or more layers of the multi-layered substrate may also provide improved barrier properties that prevent environmental contaminants from affecting the performance of a formed photovoltaic module, which includes the multi-layered substrate, during normal operation.

Abstract: Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

Abstract: A multilayer electrode on a substrate (10) comprising titanium (20) and titanium-rich titanium nitride (30) and titanium-poor titanium nitride (40), particularly suitable for the application to thermoplastic substrates, in particular for the purpose of the impedance measurement in aqueous biological media, and method for the production thereof.

Abstract: A plating device includes: an anode; a substrate holder which holds a substrate; a substrate contact which comes into contact with a peripheral edge portion of the substrate; a resistor which is disposed in a way of facing the substrate holder between the anode and the substrate holder, and is used for adjusting ion movement; and a rotation driving mechanism which causes the resistor and the substrate holder to relatively rotate. The resistor includes: a shielding region which forms an outer frame and shields the ion movement between the anode and the substrate; and a resistance region which is formed on the radially inner side of the shielding region, and has a porous structure allowing the passage of an ion. An outer diameter of the resistance region has an amplitude centering on an imaginary reference circle, and has a wave shape which is periodic and annularly continuous.

Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Abstract: A system includes a computing platform having a hardware processor, and a system memory storing a software code and a content labeling predictive model. The hardware processor is configured to execute the software code to scan a database to identify content assets stored in the database, parse metadata stored in the database to identify labels associated with the content assets, and generate a graph by creating multiple first links linking each of the content assets to its corresponding label or labels. The hardware processor is configured to further execute the software code to train, using the graph, the content labeling predictive model, to identify, using the trained content labeling predictive model, multiple second links among the content assets and the labels, and to annotate the content assets based on the second links.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a bit line structure on a top surface of the substrate; forming a spacer structure on the bit line structure, the spacer structure including a sacrificial layer sandwiched by a first dielectric layer and a second dielectric layer; removing the sacrificial layer to form a gap between the first dielectric layer and the second dielectric layer; reducing a width of the gap; and forming a seal layer to seal the gap.

Abstract: A plating apparatus includes a workpiece holder, a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.

Abstract: Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

Abstract: Provided is a semiconductor device in which the reliability of the gate insulating film in a trench gate is improved. The semiconductor device includes a semiconductor substrate, a plurality of trench gates, and a gate electrode. The semiconductor substrate includes an active region and a wiring region. The trench gates extend from the first active region to the wiring region. The trench gates form parts of transistors in the active region. The gate electrode is provided in the wiring region and is electrically connected to the trench gates. The end portions of the trench gates are located in the wiring region. The gate electrode is provided so as to cover gate contact portions formed at the end portions of the trench gates. The gate electrode is electrically connected to trench gates via the gate contact portions. The plurality of trench gates extend only in one direction.

Abstract: Provided are cleaning methods and systems to remove unintended metallic deposits from electroplating apparatuses using reverse current deplating techniques. Such cleaning involves positioning a cleaning (deplating) disk in an electroplating cup similar to a regular processed substrate. The front surface of the cleaning disk includes a corrosion resistant conductive material to form electrical connections to deposits on the cup's surfaces. The disk is sealed in the cup and submerged into a plating solution. A reverse current is then applied to the front conductive surface of the disk to initiate deplating of the deposits. Sealing compression in the cup may change during cleaning to cause different deformation of the lip seal and to form new electrical connections to the deposits. The proposed cleaning may be applied to remove deposits formed during electroplating of alloys, in particular, tin-silver alloys widely used for semiconductor and wafer level packaging.

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Abstract: Provided is an imaging unit more efficiently manufacturable with high dimensional precision. The imaging unit includes: a sensor board including an imaging device, in which the imaging device has a plurality of pixels and allows generation of a pixel signal by receiving outside light in each of the plurality of pixels; a bonding layer including an inorganic insulating material; and a circuit board including a circuit chip and an organic insulating layer, in which a circuit chip has a signal processing circuit that performs signal processing for the pixel signal and is bonded to the sensor board through the bonding layer, and the organic insulating layer covers a vicinity of the circuit chip.

Abstract: A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

Abstract: Selective deposition methods are described. An exemplary method comprises exposing the substrate comprising a first surface and a second surface to an anchor reactant and selectively depositing the anchor reactant on the first surface as a seed layer, wherein the anchor reactant comprises an ethynyl derivative with a headgroup that selectively targets the first surface.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.

Abstract: Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.

Abstract: A semiconductor device including: a silicon layer including a single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level and has a diameter of less than 450 nm, where the second level thickness is less than four microns, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

Abstract: A semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate, and a second conductive layer disposed over the first conductive layer. The semiconductor device structure also includes a first conductive plug disposed between and electrically connecting the first conductive layer and the second conductive layer. The first conductive plug includes copper. The semiconductor device structure further includes a first lining layer surrounding the first conductive plug. The first lining layer includes manganese.