Filling Of Holes, Grooves, Vias Or Trenches With Conductive Material (epo) Patents (Class 257/E21.585)
Reflowing or applying pressure to fill contact hole, e.g., to remove voids (epo) (Class 257/E21.588)
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Patent number: 11469233Abstract: The present application provides a method for preparing a memory device.Type: GrantFiled: June 25, 2020Date of Patent: October 11, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Te-Yin Chen
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Patent number: 11469176Abstract: The present disclosure relates to an electrical fuse (e-fuse) device and a method for forming the electrical fuse device. The vertical e-fuse device includes a fuse link disposed over a semiconductor base. A material of the fuse link and a material of the semiconductor base are the same. The vertical e-fuse device also includes a first bottom anode/cathode region and a second bottom anode/cathode region disposed over the semiconductor base. A bottom portion of the fuse link is sandwiched between the first bottom anode/cathode region and the second anode/cathode region. The vertical e-fuse device further includes a top anode/cathode region disposed over the fuse link.Type: GrantFiled: July 7, 2020Date of Patent: October 11, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chih-Wei Huang
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Patent number: 11462463Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.Type: GrantFiled: September 27, 2018Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
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Patent number: 11462513Abstract: A chip bonding alignment structure includes a semiconductor chip, a metal layer, an etching stop layer, at least one metal bump, a dielectric barrier layer, a silicon oxide layer, and a silicon carbonitride layer. The metal layer is disposed on a bonding surface of the semiconductor chip and has a metal alignment pattern. The etching stop layer covers the bonding surface and the metal layer. The metal bump extends upward from the metal layer and penetrates through the etching stop layer. The dielectric barrier layer covers the etching stop layer and the metal bump. The silicon oxide layer covers the dielectric barrier layer. The silicon carbonitride layer covers the silicon oxide layer.Type: GrantFiled: February 22, 2021Date of Patent: October 4, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Chia Yang, Fu-Yu Tsai, Da-Jun Lin, Bin-Siang Tsai
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Patent number: 11450561Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.Type: GrantFiled: April 22, 2020Date of Patent: September 20, 2022Assignee: Renesas Electronics CorporationInventors: Kazuyuki Omori, Seiji Muranaka, Kazuyoshi Maekawa
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Patent number: 11450635Abstract: The embodiments of the present invention discloses an arrangement of bond pads on an integrated circuit chip. The integrated circuit chip includes: a first row of bond pads; and a second row of bond pads, wherein bond pads in the first row are positioned alternately with bond pads in the second row, and a short side of the bond pads in the first row and the second row is parallel to a long side of the integrated circuit chip. With this arrangement of bond pads on the integrated circuit chip, the bond pads may occupy a reduced area of a surface of the integrated circuit chip.Type: GrantFiled: February 12, 2021Date of Patent: September 20, 2022Assignee: Changxin Memory Technologies, Inc.Inventor: Chia-Chi Hsu
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Patent number: 11430734Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.Type: GrantFiled: December 28, 2020Date of Patent: August 30, 2022Assignee: Micron Technology, Inc.Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
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Patent number: 11355404Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers.Type: GrantFiled: April 10, 2020Date of Patent: June 7, 2022Assignee: INVENSAS BONDING TECHNOLOGIES, INC.Inventors: Guilian Gao, Laura Wills Mirkarimi, Gaius Gillman Fountain, Jr.
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Patent number: 11302532Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.Type: GrantFiled: March 2, 2020Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Rasit Onur Topaloglu, Kafai Lai, Dongbing Shao, Zheng Xu
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Patent number: 11131018Abstract: A sputtering system may include a substrate. The sputtering system may include at least one target. The at least one target may include at least one coating material to coat at least one layer onto the substrate. The at least one coating material may be sputtered onto the substrate in a presence of an inert gas. The inert gas may include argon gas and helium gas.Type: GrantFiled: August 14, 2018Date of Patent: September 28, 2021Assignee: VIAVI Solutions Inc.Inventors: Andrew Clark, Georg J. Ockenfuss
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Patent number: 11049813Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.Type: GrantFiled: September 19, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
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Patent number: 10981372Abstract: A three-dimensional inkjet printer and method for printing an aperture mask on a multi-spectral filter array. A custom tray is used by the printer allowing for printing on a prefabricated filter array. Photopolymer resin is deposited on the prefabricated filter array to form the aperture mask of dark mirror coating. An ultraviolet lamp illuminates the deposited photopolymer resin on the surface of the prefabricated multi-spectral optical filter array to cure the resin, thereby forming the mask. The prefabricated multi-spectral optical filter array includes an optical coating on at least one side, the aperture mask being formed on the optical coating, without the use of heat, chemical etching, or deformation of the optical coating.Type: GrantFiled: December 11, 2018Date of Patent: April 20, 2021Assignee: Materion CorporationInventor: Kevin R. Downing
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Patent number: 10920322Abstract: The present invention relates to a method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor, the use of an acidic palladium plating bath (as defined below) for directly depositing metallic palladium or a palladium alloy onto a non-activated surface of a doped or non-doped gallium nitride semiconductor, and a palladium or palladium alloy coated, doped or non-doped gallium nitride semiconductor.Type: GrantFiled: August 21, 2017Date of Patent: February 16, 2021Assignee: Atotech Deutschland GmbHInventor: Andreas Walter
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Patent number: 10796956Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.Type: GrantFiled: June 29, 2018Date of Patent: October 6, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
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Patent number: 10672613Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.Type: GrantFiled: August 28, 2018Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Uei Jang, Chien-Hua Tseng, Chung-Shu Wu, Ya-Yi Tsai, Ryan Chia-Jen Chen, An-Chyi Wei
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Patent number: 10559497Abstract: Methods for filling a substrate feature with a seamless tungsten fill are described. The methods include depositing a tungsten film, oxidizing the tungsten film to a tungsten oxide pillar, reducing the tungsten oxide film to a seamless tungsten gapfill and optionally depositing additional tungsten on the tungsten gapfill.Type: GrantFiled: June 12, 2018Date of Patent: February 11, 2020Assignee: Applied Materials, Inc.Inventors: Yong Wu, Yihong Chen, Shishi Jiang, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
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Patent number: 10546812Abstract: A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided.Type: GrantFiled: July 13, 2018Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventor: Chih-Chao Yang
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Patent number: 10510666Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.Type: GrantFiled: February 22, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Su-Jen Sung
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Patent number: 10468596Abstract: First stacked rail structures including a first conductive rail, a selector rail, and a sacrificial material rail and separated by first trenches are formed over a substrate. First dielectric isolation structures are formed in the first trenches. Second trenches are formed, which divides the first stacked rail structures above the first conductive rails. Second dielectric isolation structures in the second trenches. Pillar structures are formed, which include a respective vertical stack of a selector element and a sacrificial material pillar. The sacrificial material pillars are replaced with phase change memory material pillars by a damascene method that deposits and planarizes a phase change memory material. Second conductive rails are formed over the phase change memory material pillars. Sidewalls of the phase change memory material pillars are not subjected to etch damage, thereby enhancing electrical characteristics of the phase change memory material pillars.Type: GrantFiled: February 21, 2018Date of Patent: November 5, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Raghuveer S. Makala, Senaka Kanakamedala, Yao-Sheng Lee
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Patent number: 10465287Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.Type: GrantFiled: March 12, 2018Date of Patent: November 5, 2019Assignees: UNITED MICROELECTRONCIS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
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Patent number: 10446469Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.Type: GrantFiled: July 22, 2016Date of Patent: October 15, 2019Assignee: Infineon Technologies AGInventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
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Patent number: 10418236Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The dielectric composite film in one embodiment includes Al, Si, and O and has a thickness of between about 10-100 ?. The dielectric composite film can reside between two layers of inter-layer dielectric, and may be in contact with metal layers. An apparatus for depositing such dielectric composite films includes a process chamber, a conduit for delivering an aluminum containing precursor to the process chamber, a second conduit for delivering a silicon-containing precursor to the process chamber and a controller having program instructions for depositing the dielectric composite film from these precursors, e.g., by reacting the precursors adsorbed to the substrate with an oxygen-containing species.Type: GrantFiled: July 17, 2018Date of Patent: September 17, 2019Assignee: Lam Research CorporationInventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
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Patent number: 10403729Abstract: A semiconductor device has a high electric connection reliability and includes a base substrate having a connection target layer, a lower contact plug formed over the base substrate and electrically connected to the connection target layer, and an upper contact plug formed over the lower contact plug, wherein the lower contact plug includes a lower plug layer having a gap portion extending inward from a top portion of the lower plug layer, a gap cover layer filling the gap portion, and an upper cover layer covering a top surface of the lower plug layer.Type: GrantFiled: December 6, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventor: Eui-bok Lee
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Patent number: 10319695Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.Type: GrantFiled: September 26, 2017Date of Patent: June 11, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
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Patent number: 10297504Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.Type: GrantFiled: August 7, 2017Date of Patent: May 21, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hui Zang, Keith Tabakman, Ruilong Xie
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Patent number: 10199342Abstract: A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.Type: GrantFiled: January 23, 2017Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xiaohua Zhan, Xinfu Liu, Yoke Leng Lim, Siow Lee Chwa
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Patent number: 10189239Abstract: A three-dimensional inkjet printer and method for printing an aperture mask on a multi-spectral filter array. A custom tray is used by the printer allowing for printing on a prefabricated filter array. Photopolymer resin is deposited on the prefabricated filter array to form the aperture mask of dark mirror coating. An ultraviolet lamp illuminates the deposited photopolymer resin on the surface of the prefabricated multi-spectral optical filter array to cure the resin, thereby forming the mask. The prefabricated multi-spectral optical filter array includes an optical coating on at least one side, the aperture mask being formed on the optical coating, without the use of heat, chemical etching, or deformation of the optical coating.Type: GrantFiled: November 15, 2016Date of Patent: January 29, 2019Assignee: MATERION CORPORATIONInventor: Kevin R. Downing
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Patent number: 10186463Abstract: An integrated electronic circuit has probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacturing including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. The process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation.Type: GrantFiled: January 25, 2016Date of Patent: January 22, 2019Assignee: STMicroelectronics S.r.l.Inventor: Alberto Pagani
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Patent number: 10157866Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.Type: GrantFiled: June 5, 2017Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 10109525Abstract: A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.Type: GrantFiled: November 21, 2017Date of Patent: October 23, 2018Assignee: United Microelectronics Corp.Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Jiunn-Hsiung Liao, Wei-Hao Huang, Kai-Teng Cheng
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Patent number: 10062647Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.Type: GrantFiled: July 11, 2017Date of Patent: August 28, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Anthony K. Stamper, Baozhen Li
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Patent number: 10049927Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.Type: GrantFiled: October 24, 2016Date of Patent: August 14, 2018Assignee: Applied Materials, Inc.Inventors: Bencherki Mebarki, Sean Kang, Keith Tatseun Wong, He Ren, Mehul B. Naik, Ellie Y. Yieh, Srinivas D. Nemani
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Patent number: 10049869Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The composite films in one embodiment include at least two elements selected from the group consisting of Al, Si, and Ge, and at least one element selected from the group consisting of O, N, and C. In one embodiment the composite film includes Al, Si and O. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) and, sequentially, with a silicon-containing compound. Adsorbed compounds are then treated with an oxygen-containing plasma (e.g., plasma formed in a CO2-containing gas) to form a film that contains Al, Si, and O.Type: GrantFiled: September 30, 2016Date of Patent: August 14, 2018Assignee: Lam Research CorporationInventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
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Patent number: 10026616Abstract: There is provided a method of reducing stress in a metal film that is highly stressed, the method including: processing the metal film by supplying a metal chloride gas containing a metal of the metal film and a reduction gas for reducing the metal chloride gas onto the metal film; and forming a process film on the metal film to reduce stress in the metal film.Type: GrantFiled: May 26, 2016Date of Patent: July 17, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Kenji Suzuki, Takanobu Hotta, Koji Maekawa, Yasushi Aiba
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Patent number: 9941196Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: April 15, 2016Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Patent number: 9922872Abstract: Processing methods comprising exposing a substrate to a nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal-containing compound and a second reactive gas to form a metal-containing film on the substrate.Type: GrantFiled: May 11, 2016Date of Patent: March 20, 2018Assignee: APPLIED MATERIALS, INC.Inventors: David Knapp, Jeffrey W. Anthis, Xinyu Fu, Srinivas Gandikota
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Patent number: 9870980Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.Type: GrantFiled: December 31, 2015Date of Patent: January 16, 2018Assignee: MEDIATEK INC.Inventors: Ming-Tzong Yang, Yu-Hua Huang, Wei-Che Huang
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Patent number: 9704803Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. In various embodiments, the method for forming a semiconductor structure includes following steps. A structure on a semiconductor substrate is received, which the structure includes at least two conductive lines and a shorting bridge, and the conductive lines electrically connected to each other through the shorting bridge. The shorting bridge is insulated to make the conductive lines electrically isolated to each other.Type: GrantFiled: September 17, 2015Date of Patent: July 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chih Yu, Chien-Mao Chen
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Patent number: 9633942Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.Type: GrantFiled: November 12, 2015Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Erik R. Hosler, Deniz E. Civay
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Patent number: 9634013Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate.Type: GrantFiled: October 16, 2014Date of Patent: April 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Jhon Jhy Liaw
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Patent number: 9627498Abstract: A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.Type: GrantFiled: May 20, 2015Date of Patent: April 18, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jia-Rong Chiou, Yu-Wei Jiang, Teng-Hao Yeh
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Patent number: 9536745Abstract: A tungsten film forming method for forming a tungsten film on a surface of a target substrate by an ALD (atomic layer deposition) method comprises adding a reduction gas to allow an ALD reaction to mainly occur when a tungsten chloride gas is supplied. In the ALD method, the tungsten chloride gas as a tungsten source gas and the reduction gas for reducing the tungsten chloride gas are alternately supplied into a chamber which accommodates the target substrate and is maintained under a depressurized atmosphere, with a purge process for purging an inside of the chamber performed between the supply of the tungsten chloride gas and the supply of the reduction gas.Type: GrantFiled: January 29, 2016Date of Patent: January 3, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Kensaku Narushima, Takanobu Hotta, Tomohisa Maruyama, Yasushi Aiba
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Patent number: 9450062Abstract: A semiconductor device includes a field effect transistor structure having source zones of a first conductivity type and body zones of a second conductivity type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die comprising the source and the body zones. The semiconductor device further includes a dielectric layer adjoining the first surface and polysilicon plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones. The polysilicon plugs have silicide crystallites in portions distant to the semiconductor die.Type: GrantFiled: January 29, 2015Date of Patent: September 20, 2016Assignee: Infineon Technologies Austria AGInventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
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Patent number: 9343357Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.Type: GrantFiled: May 9, 2014Date of Patent: May 17, 2016Assignee: QUALCOMM INCORPORATEDInventors: Jeffrey Junhao Xu, John Jianhong Zhu, Choh Fei Yeap
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Patent number: 9303788Abstract: Provided is a load lock device which includes: a container with an opening formed therein and configured to be selectively maintained at an atmospheric environment and a vacuum atmosphere; a holding unit arranged within the container and configured to hold objects to be processed; an elevation mechanism configured to vertically move the holding unit; and a pressure regulating mechanism configured to vacuum-evacuate the container through the opening of the container. The elevation mechanism includes at least two vertically-extended elevation shaft members connected to the holding unit; and a drive unit configured to vertically move the elevation shaft members. The elevation shaft members are arranged opposite each other with the opening interposed therebetween.Type: GrantFiled: November 1, 2013Date of Patent: April 5, 2016Assignee: TOKYO ELECTRON LIMITEDInventors: Masamichi Hara, Tetsuya Miyashita
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Patent number: 9275962Abstract: An integrated electronic circuit having probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacture including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation.Type: GrantFiled: May 12, 2011Date of Patent: March 1, 2016Assignee: STMicroelectronics S.r.l.Inventor: Alberto Pagani
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Patent number: 9245661Abstract: A conductive film, a method for producing the same and an array substrate comprising the same are provided, so that copper atoms can be efficiently prevented from diffusing into an adjacent semiconductor layer or interlaminated insulation film. The conductive film comprises a base film made of copper or copper alloy, in which hydrogen and/or carbon atoms are distributed.Type: GrantFiled: June 24, 2014Date of Patent: January 26, 2016Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Bin Zhang, Zhengliang Li, Zhen Liu, Luke Ding, Zhanfeng Cao, Guanbao Hui
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Patent number: 9041087Abstract: Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.Type: GrantFiled: May 27, 2014Date of Patent: May 26, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Lei Yuan, Jin Cho, Jongwook Kye
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Patent number: 9018102Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.Type: GrantFiled: February 14, 2012Date of Patent: April 28, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mohammed Radwan, Matthias Zinke
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Patent number: 9012326Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.Type: GrantFiled: April 14, 2011Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Gun Kim, Yoonjae Kim, Sungil Cho