Abstract: Microelectromechanical systems (MEMS) microphone devices and methods for packaging the same include a package substrate having an acoustic pathway therethrough that opens to an interior of the device. A MEMS microphone die having an integrated filter and a movable membrane is positioned within the interior of the device. The package substrate includes a conductive layer facing the interior of the device, and a package filter formed from the conductive layer is provided along the acoustic pathway, resulting in increased packaged MEMS microphone device yield.

Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Abstract: A method for manufacturing an LED module, including steps of: providing a heat conductive plate and an LED die, the heat conductive plate defining a concave groove therein; forming an electrode circuit layer on the heat conductive plate around the concave groove; plating one metal layer on a bottom of the concave groove of the heat conductive plate, and plating another metal layer on the LED die; eutectically bonding the metal layer of the heat conducting plate and the metal layer of the LED die together to form into an eutectic layer; forming electrodes on the LED die, and connecting the electrodes with the electrode circuit layer; and encapsulating the LED die in the concave groove.

Abstract: Methods of making a microelectromechanical system (MEMS) device are described. In some embodiments, the method includes forming a sacrificial layer over a substrate, treating at least a portion of the sacrificial layer to form a treated sacrificial portion, forming an overlying layer over at least a part of the treated sacrificial portion, and at least partially removing the treated sacrificial portion to form a cavity situated between the substrate and the overlying layer, the overlying layer being exposed to the cavity.

Abstract: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; placing a patterned layer over the substrate for substantially removing crying warpage from the substrate, the patterned layer having an opening surrounded by other openings with the substrate exposed from the patterned layer within the other openings; mounting a semiconductor chip within the opening; and attaching a component directly over the other openings, the component having a horizontal length greater than horizontal lengths of the other openings.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

Abstract: A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

Abstract: The semiconductor device 1 comprises a housing 12 which has a recess 24 in the front surface 1; a pair of lead electrodes 20 which have the distal ends 34 exposed in the recess 24, protrude from the external surface of the housing 12, and are bent along the bottom surface 16 of the housing 12; and a semiconductor element 36 which is housed in the recess 24 and is electrically connected to the pair of lead electrodes 20. The housing 12 has grooves 30 which are formed on the pair of side surfaces 18 which adjoin the front surface 14 and the bottom surface 16 on the right and left sides so as to penetrate the housing 12 from the top surface 28 toward the bottom surface 16 of the housing 12. The grooves 30 preferably have width substantially equal to the thickness of the lead electrode 20. The grooves 30 are more preferably formed to be flush with the distal ends 34 of the lead electrode 20.

Abstract: A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of openings in a carrier body, introducing an encapsulant material into each of the openings in the carrier body and cutting the carrier body to singulate the plurality of imager devices and optics modules into individual units, each of which comprise an imager device and an optics module. A device is also disclosed which includes an imager device comprising a plurality of photosensitive elements and an optics module coupled to the imager device, the optics module comprising at least one lens that, when the optics module is coupled to the imager device, is positioned a fixed, non-adjustable distance from the plurality of photosensitive elements.

Abstract: Packaged integrated devices and methods of forming the same are provided. In one embodiment, a packaged integrated device includes a package substrate, a package lid, and an integrated circuit or microelectromechanical systems (MEMS) device. The package lid is mounted to a first surface of the package substrate using an epoxy, and the package lid and the package substrate define a package interior. The package lid includes an interior coating suited to good adhesion with the epoxy, and an exterior coating suited to RF shielding, where the materials of the interior and exterior coatings are different. In one example, the interior lid coating is nickel whereas the exterior lid coating is tin.

Abstract: Disclosed are methods for forming semiconductor devices and the semiconductor devices thus obtained. In one embodiment, the method may include providing a semiconductor wafer comprising a surface, forming on the surface at least one device, forming a release layer at least in an area of the surface that encircles the at least one device, forming on the release layer at least one wall structure around the at least one device, and forming at least one cap on the at least one wall structure. In one embodiment, the device may include a substrate comprising a surface, at least one device formed on the surface, a release layer formed at least in an area of the surface that encircles the at least one device, at least one wall structure formed around the at least one device, and at least one removable cap formed on the at least one wall structure.

Abstract: A method for assembling an optically pumped solid-state laser having an extended cavity. The method includes the steps of providing a casing, mounting a TEC and a base plate in the casing, and mounting a plurality of laser components on the base plate using a UV and heat curing adhesive. Once the laser components are correctly positioned and aligned on the base plate, the adhesive is pre-cured using UV radiation. Final curing of the adhesive is obtained by subjecting the entire laser package to an ambient temperature of at least 100° C. The base plate is preferably selected to have a CTE similar to that of the laser components in order to facilitate the high temperature curing. A preferred material for the base plate is AlSiC.

Abstract: An optoelectronic component (1) is provided, having at least two connecters (2) for electrical contacting of the component (1), a housing body (3), in which the connecters (2) are embedded in places, a heat sink (4), which is connected to at least one connecter (2), wherein the housing body (3) is formed of a plastics material, the housing body (3) comprises an opening (30), in which the heat sink (4) is freely accessible in places, at least one optoelectronic semiconductor chip (5) is arranged in the opening (30) on the heat sink (4), and at least two of the connecters (2) each comprise a chip-end portion (2c), which faces the at least one optoelectronic semiconductor chip (5), wherein the chip-end portions (2c) of the at least two connecters (2) are arranged in a common plane.

Abstract: A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film.

Abstract: A method of manufacturing a protected package assembly: providing a protective modular package cover in accordance with a modular design; selectively applying an adhesive to the cross member of each subassembly receiving section of the protective modular package cover that will receive a subassembly to form an adhesive layer of the protective modular package cover; encapsulating the one or more subassemblies in the subassembly receiving sections on the selectively applied adhesive layer to generate a protected package assembly; and controlling application of a distributed downward clamping force applied to the top surfaces of the subassemblies received by the protective modular package cover and useful for mounting the protected package assembly to a core through activation of fastener elements and cross members of the subassembly receiving sections.

Abstract: Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

Abstract: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.

Abstract: A packaged device includes a package having an inner surface defining a closed internal space, a device chip fixed to the package in the internal space, and a parylene film covering at least a part of the inner surface of the package and/or at least a part of a surface of the device chip.

Abstract: A semiconductor device in which intrusion of the cutting water and cutting wastes in the singulation process can be prevented, and reliability is improved includes: a substrate; at least one semiconductor element having a piezoelectric conversion function and mounted on the main surface of the substrate; a casing fixed to the main surface of the substrate to cover the semiconductor element; a through hole formed in the substrate or the casing; and a predetermined substance filled into the through hole to close the through hole, wherein the predetermined substance has properties such that the predetermined substance wettably spreads by heating to open the through hole.

Abstract: The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits.

Abstract: Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.

Abstract: A method of forming a capped die forms a cap wafer having a top side and a bottom side. The bottom side is formed with 1) a plurality of device cavities having a first depth, and 2) a plurality of second cavities that each have a greater depth than the first depth. At least some of the plurality of second cavities each generally circumscribe at least one of the device cavities. The method then secures the cap wafer to a device wafer in a manner that causes a plurality of the device cavities each to circumscribe at least one of circuitry and structure on the device wafer. Next, the method removes at least a portion of the top side of the cap wafer to expose the second cavities. This forms a plurality of caps that each protect the noted circuitry and structure.

Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

Abstract: A semiconductor device has a base carrier with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base carrier. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base carrier and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base carrier. A portion of the second surface of the base carrier is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.

Abstract: A method is described for manufacturing a micromechanical component. The method includes providing a first substrate, forming a first connecting structure on the first substrate, and forming a microstructure on the first substrate after forming the first connecting structure. The microstructure has at least one movable functional element. The method further includes providing a second substrate having a second connecting structure, and joining the first and second substrates by carrying out a bonding process, the first and second connecting structures being joined to form a common connecting structure, and a sealed cavity being formed in the region of the microstructure. The method provides that the first connecting structure takes the form of a buried connecting structure extending up to an upper surface of the first substrate. Also described is a related micromechanical component.

Abstract: A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body. Further, a method for producing a housing for an optoelectronic component and a light emitting diode component is disclosed.

Abstract: A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip, and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant.

Abstract: This semiconductor laser apparatus includes a semiconductor laser chip and a package sealing the semiconductor laser chip. The package has a base portion mounted with the semiconductor laser chip, a sealing member and a window member. The semiconductor laser chip is sealed with the base portion, the sealing member and the window member. At least two of the base portion, the sealing member and the window member are bonded to each other through a sealant made of an ethylene-polyvinyl alcohol copolymer.

Abstract: A fabrication method of a silicon condenser microphone having an additional back chamber. The method includes applying an adhesive on a substrate and mounting a chamber container thereon by using a mounter; curing the adhesive holding the chamber container; applying an adhesive on the chamber container and mounting a micro electro mechanical system (MEMS) chip thereon by using a mounter; curing the adhesive holding the MEMS chip; and attaching the substrate on which devices are mounted to a case, wherein a back chamber formed by the chamber container is added to a back chamber of the MEMS chip. Therefore, a silicon condenser microphone fabricated by using the method may have improved sensitivity by increasing the small back chamber space of the a micro electro mechanical system (MEMS) chip itself and reduced noise including total harmonic distortion (THD).

Abstract: An electronic device includes a substrate provided with a passing opening and a MEMS device including an active surface wherein a portion of the MEMS device is integrated sensitive to chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the opening. A protective package incorporates at least partially the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device, and the opening of the substrate exposed. A barrier element is positioned in an area which surrounds the sensitive portion to realize a protection structure for the MEMS device, so that the sensitive portion is free.

Abstract: A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Abstract: Some embodiments herein relate to a transmitter. The transmitter includes an integrated circuit (IC) package including a first antenna configured to radiate a first electromagnetic signal therefrom. A printed circuit board (PCB) substrate includes a waveguide configured to receive the first electromagnetic signal and to generate a waveguide signal based thereon. A second antenna can be electrically coupled to the waveguide and can radiate a second electromagnetic signal that corresponds to the waveguide signal. Other devices and methods are also disclosed.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.

Abstract: A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer.

Abstract: A single step packaging process that both melts a solder and also cures an adhesive about a microelectronic circuit. The process finds technical advantages by simplifying packaging of a die that may be coupled to a planar flexible lead, which leads to a lower production cost and quicker manufacturing time. The planar flexible lead may be adapted to bend and flex during mechanical stress and during extreme temperature cycling, and allow direct mounting of the device to a member by easily welding or soldering. The invention may comprise a flexible solar cell diode that can be closely positioned on solar panels at an extremely low cost.

Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.

Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions (28, 30). A tuning depression (32) is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor (34) is formed on the first opposing side (24) of the first semiconductor substrate. The radio frequency conductor (34) has a first end (46) on the first portion (28) of the first semiconductor substrate (22) and a second end (48) on the second portion (30) of the first semiconductor substrate (22). A microelectronic die (78) having an integrated circuit formed therein is attached to the first opposing side (24) and the first portion (28) of the semiconductor substrate (22) such that the integrated circuit is electrically connected to the first end (46) of the radio frequency conductor (34).

Abstract: A method for manufacturing a semiconductor module, includes the steps of preparing a board; mounting a semiconductor device on the second metal foil; placing a resin case onto the board for surrounding a first metal foil, an insulating sheet, the second metal foil, and the semiconductor device; pouring a resin in a paste form into the case to fill a space relative to the first metal foil, insulating sheet, the second metal foil and the semiconductor device; and heat-curing the resin. A bottom end of a peripheral wall of the case is located above a bottom surface of the first metal. The bottom surface of the first metal foil and the resin form a flat bottom surface to contact an external mounting member.

Abstract: A method for producing a power semiconductor module including forming a contact between a contact region and a contact element as an ultrasonic welding contact via a sonotrode. The ultrasonic welding operation also being used for joining the contact regions with the contact ends and consequently for joining the contacts and the foot regions.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: The semiconductor assembly includes a first subassembly having a heat sink. Solder material is disposed on the exposed portion of a first surface of heat sink. A power semiconductor die is located on the first surface of the heat sink and is thermally coupled thereto by the solder material. A packaging patterned polymer layer is disposed on a second surface of the heat sink opposing the first surface and defines an interior surface portion of the heat sink. A semiconductor package is provided in which the first subassembly, solder material and die are located such that the interior surface portion of the second surface of the heat sink is not enclosed by the semiconductor package.

Abstract: A light emitting diode (LED) package and a method of manufacturing a LED package is provided. The LED package includes a case having first and second lead frames disposed through the case; an LED chip disposed on the case, the LED chip having first and second electrodes directly connected to the first and second lead frames through a eutectic bond, respectively; and a lens disposed over the case covering the LED chip.

Abstract: Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Abstract: A wafer having heterostructure therein is formed using a substrate with recesses formed within a dielectric layer. A magnetized magnetic layer or a polarized electret material is formed at the bottom of each recess. The magnetized magnetic layer or a polarized electret material provides a predetermined magnetic or electrical field pattern. A plurality of heterostructures is formed from on an epitaxial wafer wherein each heterostructure has formed thereon a non-magnetized magnetic layer that is attracted to the magnetized magnetic layer formed at the bottom of each recess or dielectric layer that is attracted to the polarized electret material formed at the bottom of each recess. The plurality of heterostructures is etched from the epitaxial wafer to form a plurality of heterostructure pills.

Abstract: A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.

Abstract: A packaged device includes a package having an inner surface defining a closed internal space, a device chip fixed to the package in the internal space, and a parylene film covering at least a part of the inner surface of the package and/or at least a part of a surface of the device chip.