Mounting Semiconductor Bodies In Container (epo) Patents (Class 257/E21.5)
  • Publication number: 20080023819
    Abstract: A package structure having a semiconductor chip embedded therein and a method of fabricating the same are disclosed. The package structure comprises: an aluminum oxide composite plate and a semiconductor chip. The aluminum oxide composite plate is formed by a stack consisting of an adhesive layer placed in between two aluminum oxide layers. The semiconductor chip having an active surface a plurality of electrode pads disposed thereon can be embedded and secured in the aluminum oxide composite plate. The present invention also comprises a method of fabricating the above-mentioned package structure. The present invention provides an excellent package structure, which can decrease the thickness of the package structure and make the package structure having characteristics of high rigidity and enduring tenacity at the same time.
    Type: Application
    Filed: July 24, 2007
    Publication date: January 31, 2008
    Applicant: Phoenix Precision Technology Corporation
    Inventors: Kan-Jung Chia, Shih-Ping Hsu
  • Patent number: 7320940
    Abstract: In a method for manufacturing an acceleration sensor device, a lid for covering an opening of a package body is prepared by stamping. The lid is plated and plating films are formed on surfaces of the lid. The burrs formed on the surfaces of the lid in the plating process are removed by chemical polishing. A semiconductor sensor chip is inserted in the package body through the opening and fixed. Then, the lid 70 is attached to the package body.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: January 22, 2008
    Assignees: DENSO CORPORATION, Yoshikawa Kogyo Co., Ltd.
    Inventors: Tomohito Kunda, Tsukasa Fukurai
  • Publication number: 20080009096
    Abstract: A package-on-package and a method of fabricating the same capable of increasing mounting density of a semiconductor package are provided. The method includes providing a flexible substrate first, second, and third printed circuit patterns formed on the upper and lower surfaces of the flexible substrate. First and second semiconductor chips and then respectively mounted to substantially central portions of the upper and lower surfaces of the flexible substrate and electrically connected to the first printed circuit patterns. A package body is formed by sealing the first printed circuit pattern and the semiconductor chips. Portions of the flexible substrate having the second and third printed circuit patterns are then bent towards and adhered to the upper and lower surfaces of the package body.
    Type: Application
    Filed: April 27, 2007
    Publication date: January 10, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeon HWANG
  • Publication number: 20070269929
    Abstract: A substrate, and a semiconductor die package formed therefrom, are disclosed which include a distributed plating pattern for reducing mechanical stress on the semiconductor die. The substrate according to embodiments of the invention may include traces and contact pads plated in a double image plating process. Additionally, the substrate may include dummy plating areas including plating material. The plated vias and/or traces and the plating material within the dummy plating areas provide a plating pattern which is evenly distributed across the surface of the substrate. The even distribution of the plating pattern prevents peaks and valleys in the finished substrate.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Cheemen Yu, Hem Takiar
  • Patent number: 7294915
    Abstract: An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and a composition disposed between the first substrate and the second substrate including a siloxane-based aromatic diamine.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventor: Saikumar Jayaraman
  • Patent number: 7294529
    Abstract: This publication discloses a method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. According to the invention, through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: November 13, 2007
    Assignee: Imbera Electronics Oy
    Inventor: Risto Tuominen
  • Patent number: 7285439
    Abstract: A shielding case bank has shielding cases that arranged at a pitch twice as large as a pitch of molded articles in a molded article bank. Two shielding case banks are stacked one on the other with displacement from each other by half the pitch so that the shielding cases are as a whole arranged as the same pitch as the molded articles. The stacked shielding case banks are mounted on the molded article bank so that each shielding case covers a front face, both side faces, and a top face of the corresponding molded article. Each molded article and the corresponding shielding case are fixed to each other, and a back face of each molded article is covered. After that, guide frames of the shielding case banks are sequentially separated from the shielding cases, and the molded article bank is divided into discrete molded articles.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: October 23, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Yoshida
  • Patent number: 7256067
    Abstract: An integrated circuit lid fixture and methods of using the same are provided. In one aspect, an integrated circuit lid fixture is provided that includes a base that has a plurality of pillars. Each of the plurality of pillars has a surface for supporting a substrate that may be removably seated thereon. The surfaces of the plurality of pillars have a first footprint at least as large as a footprint of the substrates to be placed thereon. A plate is provided for applying a compressive force to an integrated circuit lid positioned on any of the substrates removably seated on the pillars.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: August 14, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seah Sun Too, Tek Seng Tan, Keng Sang Cha, Kee Hean Keok
  • Publication number: 20070178629
    Abstract: A surface mount electronic device manufacturing method can produce surface mount devices at a high yield rate and high productivity by reducing warp of a circuit board. The reduced warp avoids problems in processes for dicing the circuit board. Surface mount LED devices made in accordance with the method can have high reliability and reduced non-uniformity in color tone. The method can include providing an adhesive sheet having window holes at predetermined intervals. The adhesive sheet can be adhered to the circuit board. An attachable board having window holes provided at corresponding positions to the window holes of the adhesive sheet can be adhered to the adhesive sheet. LED chips or other semiconductor devices, laser diodes, etc., can be mounted on the circuit board and located at positions corresponding to bottoms of the window holes. A thermosetting resin can be filled in the window holes for encapsulating the LED chips, etc. The surface mount devices can then be produced by dicing the circuit board.
    Type: Application
    Filed: November 7, 2006
    Publication date: August 2, 2007
    Inventors: Yoshihiro Ogawa, Kazuhiko Ueno
  • Patent number: 7229852
    Abstract: An adhesive layer containing a photo-curing adhesive and a thermosetting adhesive is formed on a semiconductor wafer in which a plurality of semiconductor elements are formed. The adhesive layer and the semiconductor wafer are adhered together by selectively exposing the adhesive layer to light and curing the photo-curing adhesive contained in the adhesive layer on the peripheral portion of each semiconductor element. By developing the photo-curing adhesive, the adhesive layer in an area that has not been exposed is removed. Whether the pattern of the adhesive layer is satisfactory or not is determined for each semiconductor element. A lid part is placed on the adhesive layer of the semiconductor element determined to be satisfactory, and the adhesive layer and the lid part are adhered together by heating the adhesive layer and causing the thermosetting adhesive contained in the adhesive layer to exhibit adhesive properties.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: June 12, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masato Hoshika
  • Patent number: 7173331
    Abstract: A hermetic sealing cap member capable of suppressing deterioration of characteristics of an electronic component resulting from a sealant such as solder coming into contact with the electronic component in a package is obtained. This hermetic sealing cap, which is a hermetic sealing cap employed for an electronic component storing package for storing an electronic component (5, 34), comprises a hermetic sealing cap member (11, 41), a first plating layer (12, 42) formed at least on a region other than a region of the hermetic sealing cap member formed with a sealant (3, 32) and a second plating layer (13, 43), formed on the region of the hermetic sealing cap member on which the sealant is arranged, containing a material superior in wettability with the sealant to the first plating layer.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 6, 2007
    Assignee: Neomax Materials Co., Ltd.
    Inventors: Shigeji Matsubara, Masaharu Yamamoto, Toshiaki Fukusako, Yoshito Tagashira
  • Patent number: 7172910
    Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to forming an assembly using different sized blocks in either a flexible or rigid substrate.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: February 6, 2007
    Assignee: Alien Technology Corporation
    Inventors: Mark A. Hadley, Ann Chiang, Gordon S. W. Craig, Jeffrey Jay Jacobsen, John Stephen Smith, Jay Tu, Roger Green Stewart
  • Patent number: 7172926
    Abstract: A method for manufacturing an adhesive substrate with a die-cavity sidewall is disclosed. A region for forming die-cavity sidewall is defined on one surface of the substrate. The substrate is laminated with a sacrificial film, a partially cured resin is formed between the substrate and the sacrificial film. And then, an aperture is routed through the substrate, the partially cured resin, and the sacrificial film. The aperture is located corresponding to the region so that the substrate has a die-cavity sidewall formed inside the aperture. Thereafter, the sacrificial film is removed to expose the partially cured resin on the substrate so that the substrate with a die-cavity sidewall can have good adhesion.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: February 6, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, Ching-Hua Tsao
  • Patent number: 7148080
    Abstract: A method for joining lead frames in a chip stack package or a package stack, a chip stack package, and a method of forming a chip stack package. A joining mediator is formed on joining portions of at least one lead frame. The joining mediator has an anti-oxidation property and an inter-metallic diffusion property, and may be formed of gold wires, gold bumps, gold bars, solder bumps, solder, or solder bars. By clamping or compressing the lead frames under heat and pressure, the joining mediator forms an inter-metallic joint layer that reliably interconnects the lead frames at the joining portions.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: December 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pyoung Wan Kim, Sang Hyeop Lee, Chang Cheol Lee, Gun Ah Lee