Involving Separation Of Active Layers From Substrate (epo) Patents (Class 257/E21.6)
  • Patent number: 11276831
    Abstract: A method of manufacturing a flexible display apparatus includes: preparing a substrate; forming a first charge adhesive layer having a first charge on the substrate; forming a second charge adhesive layer having a second charge, which is opposite to the first charge, on the first charge adhesive layer; forming a first charge adhesive pattern and a second charge adhesive pattern by removing an edge of each of the first charge adhesive layer and the second charge adhesive layer; forming a flexible substrate on the substrate on which the first charge adhesive pattern and the second charge adhesive pattern are formed; forming a display unit on the flexible substrate; cutting the substrate, the first charge adhesive pattern, the second charge adhesive pattern, the flexible substrate, and the display unit along a cutting line; and separating the substrate and the flexible substrate.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: March 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Heekyun Shin, Byunghoon Kang, Youngjun Kim, Sumin An, Woojin Cho, Seungjun Moon, Jeongmin Park, Dongkyun Seo, Junho Sim
  • Patent number: 10910272
    Abstract: A support substrate including a plurality of channels on a front side is provided. A cover layer is formed by anisotropically depositing a sacrificial cover material over the plurality of channels. Cavities laterally extend within the plurality of channels underneath a horizontally extending portion of the cover layer. An encapsulation layer is conformally deposited. First semiconductor devices, first metal interconnect structures, and first bonding pads are formed over a top surface of the encapsulation layer. A device substrate with second bonding pads is provided. The second bonding pads are bonded with the first bonding pads to form a bonded assembly. Peripheral portions of the encapsulation layer are removes and peripheral portions of the cover layer are physically exposed. The cover layer is removed employing an isotropic etch process by propagating an isotropic etchant through the cavities to separate the support substrate from the bonded assembly.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Senaka Kanakamedala, Raghuveer S Makala
  • Patent number: 9978996
    Abstract: In various exemplary embodiments, a method for producing an optoelectronic component is provided. In this case, a high temperature solid is provided which is stable at least up to a predefined first temperature. A liquid glass solder having a second temperature, which is lower than the first temperature, is applied to the high temperature solid in a structured fashion. The glass solder is solidified, as a result of which a glass solid is formed. An optoelectronic layer structure is formed above the glass solid. The glass solid and the optoelectronic layer structure form the optoelectronic component. The optoelectronic component is removed from the high temperature solid.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: May 22, 2018
    Assignee: Osram OLED GmbH
    Inventor: Thomas Wehlus
  • Patent number: 9349809
    Abstract: A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8999813
    Abstract: A method of forming a focal plane array by: forming a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer, the sensing material being a thermistor material defining at least one pixel; providing supporting legs for the pixel within the sacrificial layer, covering them with a further sacrificial layer and forming first conductive portions in the surface of the sacrificial layer that are in contact with the supporting legs; forming a second wafer having read-out integrated circuit (ROIC), the second wafer being covered by another sacrificial layer, into which is formed second conductive portions in contact with the ROIC; bringing the sacrificial oxide layers of the first wafer and second wafer together such that the first and second conductive portions are aligned and bonding them together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; and removing the sacrificial l
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 7, 2015
    Assignee: SensoNor AS
    Inventors: Adriana Lapadatu, Gjermund Kittilsland
  • Patent number: 8932938
    Abstract: A method of producing a composite structure comprises a step of producing a first layer of microcomponents on one face of a first substrate, the first substrate being held flush against a holding surface of a first support during production of the microcomponents, and a step of bonding the face of the first substrate comprising the layer of microcomponents onto a second substrate. During the bonding step, the first substrate is held flush against a second support, the holding surface of which has a flatness that is less than or equal to that of the first support used during production of the first layer of microcomponents.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: January 13, 2015
    Assignee: Soitec
    Inventors: Arnaud Castex, Marcel Broekaart
  • Patent number: 8895345
    Abstract: The present invention provides a dicing method that achieves excellent dicing properties at low costs by removing a metal film through a metal processing operation with a diamond tool and then performing pulse laser beam irradiation. The dicing method is a method of dicing a substrate to be processed, devices being formed in the substrate to be processed, a metal film being formed on one surface of the substrate to be processed.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: November 25, 2014
    Assignee: Toshiba Kikai Kabushiki Kaisha
    Inventor: Takanobu Akiyama
  • Patent number: 8790996
    Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Invensas Corporation
    Inventor: Pezhman Monadgemi
  • Patent number: 8723314
    Abstract: Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 13, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Su, Lei Fu, Edward S. Alcid
  • Patent number: 8709912
    Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 29, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yuichi Urano, Kenichi Kazama
  • Patent number: 8592291
    Abstract: A hexagonal boron nitride thin film is grown on a metal surface of a growth substrate and then annealed. The hexagonal boron nitride thin film is coated with a protective support layer and released from the metal surface. The boron nitride thin film together with the protective support layer can then be transferred to any of a variety of arbitrary substrates.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Massachusetts Institute of Technology
    Inventors: Yumeng Shi, Jing Kong, Christoph Hamsen, Lain-Jong Li
  • Patent number: 8536023
    Abstract: A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 8524573
    Abstract: A method for producing a semiconductor component, in which a semiconductor layer is separated from a substrate by irradiation with laser pulses, the pulse duration of the laser pulses being less than or equal to 10 ns. The laser pulses have a spatial beam profile with a flank slope is chosen to be gentle enough to prevent cracks in the semiconductor layer that arise as a result of thermally induced lateral stresses during the separation of semiconductor layer and substrate.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: September 3, 2013
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stephan Kaiser, Volker Härle, Berthold Hahn
  • Patent number: 8524572
    Abstract: Some embodiments include methods of processing a unit containing crystalline material. A damage region may be formed within the crystalline material, and a portion of the unit may be above the damage region. A chuck may be used to bend the unit and thereby induce cleavage along the damage region to form a structure from the portion of the unit above the damage region. Some embodiments include methods of forming semiconductor-on-insulator constructions. A unit may be formed to have dielectric material over monocrystalline semiconductor material. A damage region may be formed within the monocrystalline semiconductor material, and a portion of the monocrystalline semiconductor material may be between the damage region and the dielectric material. The unit may be incorporated into an assembly with a handle component, and a chuck may be used to contort the assembly and thereby induce cleavage along the damage region.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: September 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Ming Zhang
  • Patent number: 8482075
    Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo, Robert Robison
  • Patent number: 8470621
    Abstract: A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: June 25, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Chester Kuo, Lung Hsin Chen, Wen Liang Tseng, Shih Cheng Huang, Po Min Tu, Ying Chao Yeh, Wen Yu Lin, Peng Yi Wu, Shih Hsiung Chan
  • Patent number: 8415208
    Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: April 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Mayumi Mizukami, Shunpei Yamazaki
  • Publication number: 20130075869
    Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: Infineon Technologies AG
    Inventors: Gunther Mackh, Gerhard Leschik, Adolf Koller, Harald Seidl
  • Patent number: 8399272
    Abstract: A method of manufacturing the semiconductor light emitting element comprises a semiconductor layer forming step of forming the multilayered nitride semiconductor layer on the first wafer having a transparent property; a bonding step of bonding the multilayered nitride semiconductor layer to the first wafer; a groove forming step of forming the groove extending from the lower surface of the first wafer to the multilayered nitride semiconductor layer; a light applying step of applying a first light to the lower surface of the multilayered nitride semiconductor layer through the first wafer to reduce a bonding force between the multilayered nitride semiconductor layer and the first wafer; a separating step of separating the first wafer from the multilayered nitride semiconductor layer; and a cutting step of cutting the second wafer along the groove to divide into a plurality of the semiconductor light emitting element.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Yamae, Hiroshi Fukshima, Masaharu Yasuda, Tomoya Iwahashi, Hidenori Kamei, Syuusaku Maeda
  • Patent number: 8389381
    Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 5, 2013
    Assignee: E Ink Corporation
    Inventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
  • Patent number: 8367442
    Abstract: A method of manufacturing the semiconductor light emitting element comprises a semiconductor layer forming step of forming the multilayered nitride semiconductor layer on the first wafer having a transparent property; a bonding step of bonding the multilayered nitride semiconductor layer to the first wafer; a groove forming step of forming the groove extending from the lower surface of the first wafer to the multilayered nitride semiconductor layer; a light applying step of applying a first light to the lower surface of the multilayered nitride semiconductor layer through the first wafer to reduce a bonding force between the multilayered nitride semiconductor layer and the first wafer; a separating step of separating the first wafer from the multilayered nitride semiconductor layer; and a cutting step of cutting the second wafer along the groove to divide into a plurality of the semiconductor light emitting element.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Yamae, Hiroshi Fukshima, Masaharu Yasuda, Tomoya Iwahashi, Hidenori Kamei, Syuusaku Maeda
  • Publication number: 20120292773
    Abstract: A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 22, 2012
    Applicant: Infineon Technologies AG
    Inventors: Khalil Hosseini, Hans-Joachim Schulze
  • Patent number: 8173520
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 8, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 8137417
    Abstract: An object is to eliminate electric discharge due to static electricity generated by peeling when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element. A substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers. The film is bent along a curved surface of the pressurization roller on a side of the pressurization rollers, where the film is collected, and accordingly, peeling is generated between the element formation layer and the peeling layer and the element formation layer is transferred to the film.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8119499
    Abstract: A semiconductor substrate fabrication method according to the first aspect of this invention is characterized by including a preparation step of preparing an underlying substrate, a stacking step of stacking, on the underlying substrate, at least two multilayered films each including a peeling layer and a semiconductor layer, and a separation step of separating the semiconductor layer.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: February 21, 2012
    Assignees: Tohoku Techno Arch Co., Ltd., Furukawa Co., Ltd., Mitsubishi Chemical Corporation, Dowa Holdings Co., Ltd., Epivalley Co., Ltd., Wavesquare Inc.
    Inventors: Takafumi Yao, Meoung-Whan Cho
  • Patent number: 8088670
    Abstract: When manufacturing a bonded substrate using an insulator substrate as a handle wafer, there is provided a method for manufacturing a bonded substrate which can be readily removed after carried and after mounted by roughening a back surface of the bonded substrate (corresponding to a back surface of the insulator substrate) and additionally whose front surface can be easily identified like a process of a silicon semiconductor wafer in case of the bonded substrate using a transparent insulator substrate as a handle wafer. There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a back surface of the insulator substrate.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: January 3, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8062960
    Abstract: The present invention provides a method of manufacturing a compound semiconductor device capable of improving yield when a wafer is divided into device regions. The method of manufacturing a compound semiconductor device includes a division step. The division step includes: a first division step of dividing a wafer 30 in a first direction ? to obtain first strip wafers each having at least two rows of device portions 10 arranged in the first direction ?; a second division step of dividing the first strip wafer in a second direction ? to obtain second strip wafers each having a row of the device portions 10 arranged in the second direction ?; and a third division step of dividing the second strip wafer into the device portions 10, thereby forming compound semiconductor devices including the device portions 10.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: November 22, 2011
    Assignee: Showa Denko K.K.
    Inventor: Kazuhiro Kato
  • Patent number: 8021964
    Abstract: To provide a method of producing segmented chips preventing the chips from being damaged by the chip jumping or by the contact of the neighboring chips while the back surfaces thereof are being ground.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: September 20, 2011
    Assignee: 3M Innovative Properties Company
    Inventors: Ryota Akiyama, Kazuta Saito
  • Patent number: 8012854
    Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: September 6, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 7994025
    Abstract: A wafer processing method of processing a wafer having on a front surface a device area where a plurality of devices are formed by being sectioned by predetermined dividing lines, and an outer circumferential redundant area surrounding the device area, includes the steps of: sticking a protection tape to the front surface of the wafer; holding a protection tape side of the wafer by a rotatable chuck table, positioning a cutting blade on a rear surface of the wafer, and rotating the chuck table to cut a boundary portion between the device area and the outer circumferential redundant area to form a separation groove; grinding only the rear surface of the wafer corresponding to the device area to form a circular recessed portion to leave the ring-like outer circumferential redundant area as a ring-like reinforcing portion, the wafer being such that the device area and the ring-like outer circumferential redundant area are united by the protection tape; and conveying the wafer supported by the ring-like reinforci
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: August 9, 2011
    Assignee: Disco Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 7989304
    Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 2, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Patent number: 7955969
    Abstract: Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventors: Daniel M. Kinzer, Michael A. Briere, Alexander Lidow
  • Patent number: 7951687
    Abstract: An electrical element, such as a thin-film transistor, is defined on a flexible substrate, in that the substrate is attached to a carrier by an adhesive layer, and is delaminated after definition of the transistor. This is for instance due to illumination by UV-radiation. An opaque coating is provided to protect any semiconductor material. A heat treatment is preferably given before application of the layers of the transistor to reduce stress in the adhesive layer.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: May 31, 2011
    Assignee: Polymer Vision Limited
    Inventors: Jacobus Bernardus Giesbers, Monique Johanna Beenhakkers, Cornelis Johannus Hermanus Antonius Rijpert, Gerwin Hermanus Gelinck, Fredericus Johannes Touwslager
  • Patent number: 7932111
    Abstract: A method for fabricating light emitting diode (LEDs) comprises providing a plurality of LEDs on a substrate wafer, each of which has an n-type and p-type layer of Group-III nitride material formed on a SiC substrate with the n-type layer sandwiched between the substrate and p-type layer. A conductive carrier is provided having a lateral surface to hold the LEDs. The LEDs are flip-chip mounted on the lateral surface of the conductive carrier. The SiC substrate is removed from the LEDs such that the n-type layer is the top-most layer. A respective contact is deposited on the n-type layer of each of the LEDs and the carrier is separated into portions such that each of the LEDs is separated from the others, with each of the LEDs mounted to a respective portion of said carrier.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: April 26, 2011
    Assignee: Cree, Inc.
    Inventor: John Edmond
  • Patent number: 7897482
    Abstract: A separation layer containing a halogen element is formed over a glass substrate by a plasma CVD method; a semiconductor element is formed over the separation layer; and separation is then performed inside the separation layer or at its interface, so that the large-area glass substrate and the semiconductor element are detached from each other. In order to perform detachment at the interface between the glass substrate and the separation layer, the separation layer may have concentration gradient of the halogen element, and the halogen element is contained more near the interface between the separation layer and the glass substrate than in the other areas.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoshi Toriumi
  • Patent number: 7892867
    Abstract: A carrier applicable to a laser releasing process and for carrying at least a flexible display panel is provided. The flexible display panel is formed on a transparent substrate and includes a display main body and a driving circuit module connected to an edge of the display main body. The carrier includes a carrying plate having at least a carrying area for carrying the flexible display panel and a protecting cover disposed on the carrying plate and located at an edge of the carrying area. A receiving space is formed between the protecting cover and the carrying plate for receiving the driving circuit module. The protecting cover is for shielding the driving circuit module to prevent the driving circuit module from being irradiated by a laser beam in the laser releasing process. A method for manufacturing flexible display panel also is provided.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: February 22, 2011
    Assignee: E Ink Holdings Inc.
    Inventors: Ted-Hong Shinn, Hung-Pin Su, Jui-Chung Cheng, Yi-Ching Wang
  • Patent number: 7875510
    Abstract: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a support layer of mainly clay containing silicate mineral having a layered crystal structure on the separation layer, forming a thin-film functional member on the support layer, applying an energy to the separation layer to reduce the adhesion between the substrate and the support layer, and removing the substrate from the support layer and the thin-film functional member.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 25, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Katsuyoshi Onodera
  • Patent number: 7867805
    Abstract: Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process that allows one to structure any complex structured layer stacks, where the layers can be applied on top of each other using, e.g., bonding technology.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Rainer Krause, Markus Schmidt
  • Patent number: 7791190
    Abstract: An array of crystalline silicon dies on a substrate and a method for yielding the array are provided. The method comprises: delineating an array of die areas on a crystalline semiconductor wafer; implanting the die areas with hydrogen ions; overlying the die areas with a layer of polymer to form, for each die, an aggregate including a die area first wafer layer; polymerically bonding an optically clear carrier to the die areas; thermally annealing the wafer to induce breakage in the wafer; forming, for each die, an aggregate wafer second layer with a thickness less than the die thickness; and, for each die, conformably attaching the aggregate wafer second layer to a substrate. The substrate can have an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than and equal to approximately 20 nanometers.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: September 7, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: James S. Flores, Yutaka Takafuji, Steven R. Droes
  • Patent number: 7785988
    Abstract: A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: August 31, 2010
    Assignee: E Ink Corporation
    Inventors: Karl R. Amundson, Guy M. Danner, Gregg M. Duthaler, Peter T. Kazlas, Yu Chen, Kevin L. Denis, Nathan R. Kane, Andrew P. Ritenour
  • Publication number: 20100216295
    Abstract: Methods and apparatus for producing a semiconductor on glass (SOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing at least one cleaved surface; subjecting the at least one cleaved surface to an amorphization ion implantation process at a dose sufficient to amorphize at least some depth of the semiconductor material below the at least one cleaved surface; and re-growing the amorphized portion of the semiconductor material into a substantially single crystalline semiconductor layer using solid phase epitaxial re-growth
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Inventor: Alex Usenko
  • Patent number: 7749829
    Abstract: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: July 6, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gauri V. Karve, Debby Eades, Gregory S. Spencer, Ted R. White
  • Publication number: 20100167437
    Abstract: The present invention provides a simplifying method for a peeling process as well as peeling and transcribing to a large-size substrate uniformly. A feature of the present invention is to peel a first adhesive and to cure a second adhesive at the same time in a peeling process, thereby to simplify a manufacturing process. In addition, the present invention is to devise the timing of transcribing a peel-off layer in which up to an electrode of a semiconductor are formed to a predetermined substrate. In particular, a feature is that peeling is performed by using a pressure difference in the case that peeling is performed with a state in which plural semiconductor elements are formed on a large-size substrate.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 1, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toru TAKAYAMA, Junya MARUYAMA, Yuugo GOTO, Yumiko OHNO
  • Patent number: 7736948
    Abstract: Individual devices (100) are locally attached to a carrier substrate (10), so that they can be removed therefrom individually. This is achieved through the use of a patterned release layer, particularly a layer that is removable through decomposition into gaseous or vaporized decomposition products. The mechanical connection between the carrier substrate (10) and the individual devices (100) is provided by a bridging portion (43) of an adhesion layer (40).
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: June 15, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ronald Dekker, Greja Johanna Adriana Maria Verheijden, Theodorus Martinus Michielsen, Carel Van Der Poel, Cornelis Adrianus Henricus Antonius Mutsaers
  • Patent number: 7709283
    Abstract: The invention provides a semiconductor device, a method of manufacturing the same, an electro-optic device and an electronic apparatus which are capable of addressing or solving a problem of mechanical mounting of a semiconductor element chip on a substrate. A semiconductor device includes a tile-shaped microelement bonded to a substrate, and an insulating functional film provided to cover at least a portion of the tile-shaped microelement.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Takayuki Kondo
  • Patent number: 7678668
    Abstract: It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=?/2n×m±? (nm), when a light wavelength is ? (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0???10 is satisfied.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 16, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hideto Ohnuma, Tetsuya Kakehata, Kenichiro Makino
  • Publication number: 20090315045
    Abstract: An integrated compound semiconductor light-emitting-device capable of emitting light as a large-area plane light source, exhibiting excellent in-plane uniformity in an emission intensity is provided. The light-emitting-device comprising a plurality of light-emitting-units formed over a substrate, wherein the light-emitting-unit has a compound semiconductor thin-film crystal layer 24, 25, 26 a first and a second-conductivity-type-side electrode 27, 28; a main light-extraction direction is the side of the substrate, and the first and the second-conductivity-type-side electrode are formed on the opposite side to the light-extraction direction; the light-emitting-units are electrically separated each other by a light-emitting-unit separation-trench which is formed by removing the thin-film crystal layer from the surface to an inside portion of the buffer layer.
    Type: Application
    Filed: April 30, 2007
    Publication date: December 24, 2009
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventor: Hideyoshi Horie
  • Publication number: 20090273061
    Abstract: A double-structure silicon on insulator (SOI) substrate with a silicon layer, an insulation film (silicon oxide film), a silicon layer, and an insulation film in this order from the side of the surface. The upper-layer insulation film is formed so as to have a uniform distribution of depth while the lower-layer insulation film is formed so as to have a non-uniform distribution of depth so that a thick portion may be formed in the silicon layer along a predetermined path. The refractive index of Si is 3.5 and the refractive index of SiO2 is 1.5. The thick portion of the silicon layer provides a core and the insulation films corresponding to this thick portion provide clads, thereby forming an optical waveguide along the predetermined path. The silicon layer at the side of the surface has a uniform thickness, thereby enabling characteristics of MOS devices fabricated on various portions of the silicon layer to be met with each other easily and facilitating a design of the electrical device as a whole.
    Type: Application
    Filed: November 17, 2006
    Publication date: November 5, 2009
    Applicant: SONY CORPORATION
    Inventor: Koichiro Kishima
  • Patent number: 7611965
    Abstract: It is an object of the present invention to manufacture, with high yield, semiconductor devices in each of which an element which has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming an element-forming layer by forming an inorganic compound layer, a first conductive layer, and a layer containing an organic compound over the separation layer, and forming a second conductive layer which is in contact with the layer containing an organic compound and the inorganic compound layer; and after attaching a first flexible substrate over the second conductive layer, separating the separation layer and the element-forming layer at the separation layer.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: November 3, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsunenori Suzuki, Ryoji Nomura, Mikio Yukawa, Nobuharu Ohsawa, Tamae Takano, Yoshinobu Asami, Takehisa Sato
  • Patent number: 7595256
    Abstract: It is an object of the invention to provide a lightweight semiconductor device having a highly reliable sealing structure which can prevent ingress of impurities such as moisture that deteriorate element characteristics, and a method of manufacturing thereof. A protective film having superior gas barrier properties (which is a protective film that is likely to damage an element if the protective film is formed on the element directly) is previously formed on a heat-resistant substrate other than a substrate with the element formed thereon. The protective film is peeled off from the heat-resistant substrate, and transferred over the substrate with the element formed thereon so as to seal the element.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: September 29, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Yuugo Goto, Yumiko Fukumoto, Junya Maruyama, Takuya Tsurume