Involving Separation Of Active Layers From Substrate (epo) Patents (Class 257/E21.6)
  • Publication number: 20090181514
    Abstract: A heat treatment apparatus is disclosed, which enables suppression of a warp of a base substrate to which a plurality of single crystal semiconductor substrates are bonded. An example of the apparatus comprises a treatment chamber, a supporting base provided in the treatment chamber, a plurality of supports which are provided over the supporting base and are arranged to support the base substrate, and a heating unit for heating the base substrate, where each position of the plurality of supports can be changed over the supporting base. The use of this apparatus contributes to the reduction in the region where the base substrate and the supports are in contact with each other, which allows uniform heating of the base substrate, leading to the formation of an SOI substrate with high quality.
    Type: Application
    Filed: January 8, 2009
    Publication date: July 16, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei YAMAZAKI
  • Patent number: 7531430
    Abstract: The invention relates to a process of treating a structure for electronics or optoelectronics, wherein the structure that has a substrate, a first oxide layer, an intermediate layer, a second oxide layer made of an oxide of a semiconductor material, and a thin semiconductor layer made of the semiconductor material. The process includes a heat treatment of the structure in an inert or reducing atmosphere with a temperature and a duration chosen for inciting an amount of oxygen of the second oxide layer to diffuse through the semiconductor layer so that the thickness of the second oxide layer decreases by a determined value. The invention also relates to a process of manufacturing a structure for electronics or optoelectronics through the use of this type of heat treatment.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 12, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Oleg Kononchuk
  • Patent number: 7479442
    Abstract: Provided is a method of manufacturing a single crystal Si film. The method includes: preparing a Si substrate on which a first oxide layer is formed and an insulating substrate on which a second oxide layer is formed; forming a dividing layer at a predetermined depth from a surface of the Si substrate by implanting hydrogen ions from above the first oxide layer; bonding the insulating substrate to the Si substrate so that the first oxide layer contacts the second oxide layer; and forming a single crystal Si film having a predetermined thickness on the insulating substrate by cutting the dividing layer by irradiating a laser beam from above the insulating substrate. Therefore, a single crystal Si film having a predetermined thickness can be formed on an insulating substrate.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: January 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Noguchi, Wenxu Xianyu, Huaxiang Yin
  • Patent number: 7476596
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 13, 2009
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Publication number: 20080242051
    Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.
    Type: Application
    Filed: March 14, 2008
    Publication date: October 2, 2008
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
  • Publication number: 20080237804
    Abstract: A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.
    Type: Application
    Filed: October 16, 2007
    Publication date: October 2, 2008
    Inventors: Konstantin BOURDELLE, Nguyet-Phuong Nguyen, Walter Schwarzenbach
  • Patent number: 7420263
    Abstract: An array of grooves (23) is formed in a first side (12) of a wafer (10) during a wafer processing method. A back grinding tape (16) is adhered to the first side. An amount of material is removed from the second side (20) of the wafer. An adhesive layer (30) is applied to the second side. Dicing tape (24) is applied to the adhesive layer to create a first wafer assembly (32). The first wafer assembly is supported on a support surface (34) with the dicing tape facing the support surface and the back grinding tape exposed. The back grinding tape is removed and the adhesive layer is severed through the array of grooves to create individually removable die (28).
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: September 2, 2008
    Assignee: ChipPAC, Inc.
    Inventors: Seung Wook Park, Hyun Jin Park
  • Patent number: 7387947
    Abstract: The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: June 17, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Ian Cayrefourcq, Carlos Mazure, Konstantin Bourdelle
  • Patent number: 7387946
    Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: June 17, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thuy Dao
  • Patent number: 7364958
    Abstract: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Alexander Reznicek, Min Yang
  • Patent number: 7351644
    Abstract: A method for fabricating one or more devices, e.g., integrated circuits. The method includes providing a substrate (e.g., silicon), which has a thickness of semiconductor material and a surface region. The substrate also has a cleave plane provided within the substrate to define the thickness of semiconductor material. The method includes joining the surface region of the substrate to a first handle substrate. In a preferred embodiment, the first handle substrate is termed a “thin” substrate, which provides suitable bonding characteristics, can withstand high temperature processing often desired during the manufacture of semiconductor devices, and has desirable de-bonding characteristics between it and a second handle substrate, which will be described in more detail below. In a preferred embodiment, the first handle substrate is also thick enough and rigid enough to allow for cleaving according to a specific embodiment.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: April 1, 2008
    Assignee: Silicon Genesis Corporation
    Inventor: Francois J. Henley
  • Patent number: 7341925
    Abstract: A method for transferring a semiconductor body selected from the group consisting of a semiconductor layer, a semiconductor layer sequence or a semiconductor layer structure from a growth substrate to a support material. An interface between the growth substrate and the semiconductor body or a region in the vicinity of the interface is exposed to electromagnetic radiation through one of the semiconductor body and the growth substrate. A material at or in proximity to the interface is decomposed by absorption of the electromagnetic radiation in proximity to or at the interface so that the semiconductor body can be separated from the growth substrate. The semiconductor body is connected to the support material.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: March 11, 2008
    Assignee: Osram GmbH
    Inventors: Michael Kelly, Oliver Ambacher, Martin Stutzmann, Martin Brandt, Roman Dimitrov, Robert Handschuh
  • Patent number: 7307006
    Abstract: It is an object of the present invention to provide a technology to manufacture a semiconductor sheet or a semiconductor chip with a high yield using a circuit having a thin film transistor. A manufacturing method for a semiconductor device comprises: attaching a flexible base material to an element layer x times (x is an integer number of 4 or more), wherein a thickness of a base material which is attached to the element layer (y+1)th (y is an integer number of 1 or more and less than x) time is the same or smaller than that of a base material which is attached to the element layer y-th (y is an integer number of 1 or more and less than x) time.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Susumu Okazaki, Nozomi Horikoshi
  • Patent number: 7279401
    Abstract: A method of fabricating a flexible thin film transistor array substrate is provided. First, a rigid substrate is provided, and a polymer material layer is coated on the rigid substrate. Then, an insulating layer is coated over the polymer material layer by a spin coating process. The insulating layer covers the sides of the polymer material layer. Thereafter, a thin film transistor array is formed over the insulating layer. Then, the polymer material layer having the thin film transistor array is separated from the rigid substrate.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: October 9, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Te-chi Wong, Jian-Shu Wu, Horng-Long Tyan, Chyi-Ming Leu
  • Patent number: 7256443
    Abstract: A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: August 14, 2007
    Assignee: Innotech Corporation
    Inventor: Takashi Miida
  • Patent number: 7169682
    Abstract: A method for manufacturing a semiconductor device comprising: a first step of successively forming a silicon oxide film and a silicon nitride film on a silicon substrate, followed by forming a silicon nitride oxide film or a multilayered film containing the silicon nitride oxide film on the silicon nitride film; a second step of forming a photoresist film having an opening portion located at the position corresponding to an element isolation area of the silicon substrate on the silicon nitride film or the multilayered film according to a photolithography method; a third step of forming a trench having a pair of tapered side surface portions on the confronting side surfaces thereof on the silicon nitride oxide film or the multilayered film by using the photoresist film as a mask, the tapered side surface portions being inclined toward the substrate side so as to approach each other; and a fourth step of patterning the silicon nitride film and the silicon oxide film by dry etching by using the photoresist fi
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: January 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuhiro Hirohama, Masaru Tanaka, Takayoshi Hashimoto, Shinichi Sato, Hideyuki Kanzawa
  • Patent number: 7163875
    Abstract: The invention relates to an object (1) that is cut by means of a laser and a water beam and to further processing of the cut material. The object is glued on a carrier (3) that is provided with an adhesive and can be transparent for the radiation used in the water beam (7). The carrier can be a solid body and preferably a fibrous mat (3). Said body or mat is penetrated by the water beam. The object (1) or the cut material thereof is held on the carrier (3) before, during and after cutting through in such a way that said object or material does not change position. In a preferred embodiment, a silicon wafer is used as the object because of the high cutting exactness to be obtained. Other materials can also be used.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: January 16, 2007
    Assignee: Synova S.A.
    Inventor: Bernold Richerzhagen
  • Patent number: 7157352
    Abstract: A method for producing an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality. The method uses two porous peeling layers on opposite sides of a substrate to produce an ultra-thin substrate.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: January 2, 2007
    Assignee: Sony Corporation
    Inventor: Hideo Yamanaka
  • Patent number: 7125796
    Abstract: A process is provided for fabricating a via 52 between bonded wafers without undercutting an organic bonding material 32. The process for forming the via 52 in a structure including a dielectric material 14 and an organic bonding material 32, comprises forming a resist material 42 on the dielectric layer 14 and etching through the dielectric layer 14 and the organic bonding material 32 with 60CF4/20Ar/60CHF3/20N2. The resist may then be removed with an anisotropic high density oxygen plasma.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: October 24, 2006
    Assignee: Motorola, Inc.
    Inventors: Donald F. Weston, William J. Dauksher, Ngoc V. Le