With Particular Manufacturing Method Of Channel, E.g., Channel Implants, Halo Or Pocket Implants, Or Channel Materials (epo) Patents (Class 257/E21.633)
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Patent number: 8658543Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.Type: GrantFiled: February 7, 2012Date of Patent: February 25, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Joanna Wasyluk, Stephan Kronholz, Yew-Tuck Chow, Richard J. Carter, Berthold Reimer, Kai Tern Sih
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Patent number: 8653604Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.Type: GrantFiled: September 21, 2012Date of Patent: February 18, 2014Assignee: SuVolta, Inc.Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
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Patent number: 8647939Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.Type: GrantFiled: August 20, 2013Date of Patent: February 11, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
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Patent number: 8647951Abstract: Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.Type: GrantFiled: August 24, 2011Date of Patent: February 11, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
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Patent number: 8637938Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.Type: GrantFiled: December 2, 2010Date of Patent: January 28, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Akihiro Usujima
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Patent number: 8629016Abstract: Multiple transistor types are formed in a common epitaxial layer by differential out-diffusion from a doped underlayer. Differential out-diffusion affects the thickness of a FET channel, the doping concentration in the FET channel, and distance between the gate dielectric layer and the doped underlayer. Differential out-diffusion may be achieved by differentially applying a dopant migration suppressor such as carbon; differentially doping the underlayer with two or more dopants having the same conductivity type but different diffusivities; and/or differentially applying thermal energy.Type: GrantFiled: April 30, 2012Date of Patent: January 14, 2014Assignee: SuVolta, Inc.Inventors: Thomas Hoffmann, Pushkar Ranade, Lucian Shifren, Scott E. Thompson
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Publication number: 20130323892Abstract: One illustrative method disclosed herein involves forming first and second gate structures that include a cap layer for a first transistor device and a second transistor device, respectively, wherein the first and second transistors are oriented transverse to one another, performing a first halo ion implant process to form first halo implant regions for the first transistor with the cap layer in position in the first gate structure of the first transistor, removing the cap layer from at least the second gate structure of the second transistor and, after removing the cap layer, performing a second halo ion implant process to form second halo implant regions for the second transistor, wherein the first and second halo implant processes are performed at transverse angles relative to the substrate.Type: ApplicationFiled: June 4, 2012Publication date: December 5, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
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Patent number: 8592270Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.Type: GrantFiled: May 25, 2011Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Douglas C. La Tulipe, Jr.
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Patent number: 8580637Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.Type: GrantFiled: December 16, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhun Hua Chen, Yu-Lung Tung, Chi-Tien Chen, Hua-Tai Lin, Hsiang-Lin Chen, Hung Chang Hsieh, Yi-Fan Chen
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Patent number: 8569858Abstract: An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.Type: GrantFiled: December 20, 2006Date of Patent: October 29, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Vance H. Adams, Paul A. Grudowski
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Patent number: 8557648Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.Type: GrantFiled: January 11, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 8530303Abstract: A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.Type: GrantFiled: September 23, 2011Date of Patent: September 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Chul-Sung Kim, Yu-Gyun Shin, Dae-Yong Kim, Joon-Gon Lee, Kwang-Young Lee
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Patent number: 8531010Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.Type: GrantFiled: November 3, 2010Date of Patent: September 10, 2013Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Kazuhiro Nojima
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Patent number: 8519403Abstract: A method for forming a submicron device includes depositing a hard mask over a first region that includes a polysilicon well of a first dopant type and a gate of a second dopant type and a second region that includes a polysilicon well of a second dopant type and a gate of a first dopant type. The hard mask over the first region is removed. Angled implantation of the first dopant type is performed to form pockets under the gate of the second dopant type.Type: GrantFiled: February 4, 2011Date of Patent: August 27, 2013Assignee: Altera CorporationInventors: Che Ta Hsu, Christopher J. Pass, Dale Ibbotson, Jeffrey T. Watt, Yanzhong Xu
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Patent number: 8513765Abstract: A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.Type: GrantFiled: July 19, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
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Patent number: 8513074Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. On the other hand, increased yield losses observed in conventional strategies may be reduced by taking into consideration the increased etch rate of the carbon-doped silicon material in the active regions. To this end, the carbon species may be incorporated after the application of at least some aggressive wet chemical processes.Type: GrantFiled: May 5, 2011Date of Patent: August 20, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Peter Javorka, Stephan Kronholz
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Patent number: 8486783Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.Type: GrantFiled: February 11, 2010Date of Patent: July 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Woong-hee Sohn, Byung-hee Kim, Dae-yong Kim, Min-sang Song, Gil-heyun Choi, Kwang-jin Moon, Hyun-su Kim, Jang-hee Lee, Eun-ji Jung, Eun-ok Lee
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Patent number: 8481341Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.Type: GrantFiled: June 4, 2012Date of Patent: July 9, 2013Assignee: Tokyo Electron LimitedInventor: Robert D. Clark
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Patent number: 8445969Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.Type: GrantFiled: April 27, 2011Date of Patent: May 21, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Xiangdong Chen, Laegu Kang, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony
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Publication number: 20130119473Abstract: A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Unoh Kwon, Ramachandran Muralidhar, Viorel Ontalus
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Patent number: 8440530Abstract: In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer.Type: GrantFiled: October 18, 2011Date of Patent: May 14, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Stefan Flachowsky, Shiang Yang Ong
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Publication number: 20130115721Abstract: A method of fabricating a semiconductor device. A substrate is provided and includes a dielectric layer and a mask layer, which is patterned and developed. A plurality of trenches is created within the dielectric material by a retrograde etching process. The plurality of trenches is subsequently overfilled with a material by heteroepitaxial growth with aspect ratio trapping. The material includes at least one of germanium, a Group III-V compound, or a combination of two or more thereof. The overfilled plurality of trenches is then planarized.Type: ApplicationFiled: June 4, 2012Publication date: May 9, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: Robert D. Clark
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Publication number: 20130109141Abstract: A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Inventors: Da Zhang, Konstantin V. Loiko, Spencer E. Williams, Brian A. Winstead
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Patent number: 8431496Abstract: A threshold voltage of a thin film transistor is adjusted. The thin film transistor is manufactured through the steps of: introducing a semiconductor material gas into a treatment chamber; forming a semiconductor film in the treatment chamber over a gate insulating layer provided covering a gate electrode; evacuating the semiconductor material gas in the treatment chamber; introducing rare gas into the treatment chamber; performing plasma treatment on the semiconductor film in the treatment chamber; forming an impurity semiconductor film over the semiconductor film; processing the semiconductor film and the impurity semiconductor film into island shapes, so that a semiconductor stack is formed; forming source and drain electrodes in contact with an impurity semiconductor layer included in the semiconductor stack. Argon is preferably used as the rare gas. The rare gas element is preferably contained in the semiconductor film at 2.5×1018 cm?3 or more.Type: GrantFiled: February 25, 2011Date of Patent: April 30, 2013Assignee: Semiconductor Energy Labortory Co., Ltd.Inventor: Satoshi Toriumi
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Publication number: 20130095620Abstract: In one example, a method disclosed herein includes the steps of forming a first liner layer above a substrate and above gate structures for both a PMOS transistor and an NMOS transistor, and, after forming extension implant regions and halo implant regions, forming a first spacer proximate the gate structures of both the PMOS and NMOS transistors, forming deep source/drain implant regions in the substrate for the PMOS and NMOS transistors, removing the first spacer and, after removing the first spacer, forming a layer of material between the adjacent gate structures, wherein the layer of material occupies at least the space formerly occupied by the first spacer.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Jan Hoentschel, Stefan Flachowsky, Shiang Yang Ong
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Patent number: 8409975Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.Type: GrantFiled: December 29, 2011Date of Patent: April 2, 2013Assignee: Shanghai Huali Microelectronics CorporationInventor: Liujiang Yu
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Patent number: 8405148Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.Type: GrantFiled: July 18, 2011Date of Patent: March 26, 2013Assignee: Volterra Semiconductor CorporationInventors: Budong You, Marco A. Zuniga
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Publication number: 20130065367Abstract: In one example, a method disclosed herein includes the steps of forming gate electrode structures for a PMOS transistor and for an NMOS transistor, forming a first spacer proximate the gate electrode structures, after forming the first spacer, forming extension implant regions in the substrate for the transistors and after forming the extension implant regions, forming a second spacer proximate the first spacer for the PMOS transistor. This method also includes performing an etching process with the second spacer in place to define a plurality of cavities in the substrate proximate the gate structure for the PMOS transistor, removing the first and second spacers, forming a third spacer proximate the gate electrode structures of both of the transistors, and forming deep source/drain implant regions in the substrate for the transistors.Type: ApplicationFiled: September 13, 2011Publication date: March 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Thilo Scheiper, Ricardo P. Mikalo
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Publication number: 20130059421Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.Type: ApplicationFiled: September 27, 2012Publication date: March 7, 2013Inventor: Wesley H. Morris
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Patent number: 8377772Abstract: Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (VT) of each of the I/O NMOS transistor and the I/O PMOS transistor to a desired level. Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and I/O PMOS transistors masked without affecting the set/adjusted VT of the I/O transistors.Type: GrantFiled: August 17, 2010Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: Weize Xiong, Greg Charles Baldwin
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Patent number: 8324034Abstract: In a method of manufacturing a display device, a first insulating layer is formed on a semiconductor pattern. Ions of a first concentration are injected into source and drain domains of the semiconductor pattern and a lower electrode of the semiconductor pattern by using a mask pattern that selectively overlaps a channel domain of the semiconductor pattern and is positioned on the top of the first insulating layer. The mask pattern is removed. An ion injection process of injecting ions of a second concentration lower than the first concentration into the semiconductor pattern of the channel domain is directly performed in the first insulating layer. A gate electrode that overlaps the channel domain is formed on the top of the first insulating layer. An upper electrode that overlaps the lower electrode is formed on the top of the first insulating layer.Type: GrantFiled: August 16, 2010Date of Patent: December 4, 2012Assignee: Samsung Display Co., Ltd.Inventor: Hyun-Uk Oh
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Publication number: 20120302019Abstract: A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Douglas C. La Tulipe, JR.
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Patent number: 8318559Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.Type: GrantFiled: October 19, 2010Date of Patent: November 27, 2012Assignee: United Microelectronics Corp.Inventors: Ming-I Chen, Fang-Mei Chao
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Publication number: 20120282744Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. On the other hand, increased yield losses observed in conventional strategies may be reduced by taking into consideration the increased etch rate of the carbon-doped silicon material in the active regions. To this end, the carbon species may be incorporated after the application of at least some aggressive wet chemical processes.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Peter Javorka, Stephan Kronholz
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Patent number: 8304305Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.Type: GrantFiled: June 8, 2011Date of Patent: November 6, 2012Assignee: Infineon Technologies Austria AGInventors: Davide Chiola, Carsten Schaeffer
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Publication number: 20120273894Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC.Inventors: Xiangdong Chen, Laegu Kang, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony
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Patent number: 8299471Abstract: The invention discloses an organic electroluminescent device includes a substrate. The substrate includes a first control area and a second control area, a polysilicon active layer disposed on the first control area, and a first conductivity type source/drain area disposed in the polysilicon active layer. A first dielectric layer is disposed on the polysilicon active layer serving as a first gate dielectric layer, a first gate and a second gate is disposed on the polysilicon active layer and the second control area, respectively, wherein the first gate and the first conductivity type source/drain area constitute a first conductivity type thin film transistor serving as a switch element. A second dielectric layer disposed on the first gate and the second gate serves as a second gate dielectric layer, a micro-crystal silicon active layer disposed over the second gate.Type: GrantFiled: January 27, 2009Date of Patent: October 30, 2012Assignee: Chimei Innolux CorporationInventors: Hanson Liu, Ryan Lee, Chun-Hsiang Fang
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Patent number: 8299538Abstract: Disclosed are embodiments of an integrated circuit structure with field effect transistors having differing divot features at the isolation region-semiconductor body interfaces so as to provide optimal performance versus stability (i.e., optimal drive current versus leakage current) for logic circuits, analog devices and/or memory devices. Also disclosed are embodiments of a method of forming the integrated circuit structure embodiments. These method embodiments incorporate the use of a cap layer pullback technique on select semiconductor bodies and subsequent wet etch process so as to avoid (or at least minimize) divot formation adjacent to some but not all semiconductor bodies.Type: GrantFiled: August 20, 2010Date of Patent: October 30, 2012Assignee: Internantional Business Machines CorporationInventors: Brent A. Anderson, Suk Hoon Ku, Edward J. Nowak
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Publication number: 20120267683Abstract: Devices are formed with an oxide liner and nitride layer before forming eSiGe spacers. Embodiments include forming first and second gate stacks on a substrate, forming an oxide liner over the first and second gate stacks, forming a nitride layer over the oxide liner, forming a resist over the first gate stack, forming nitride spacers from the nitride layer over the second gate stack, forming eSiGe source/drain regions for the second gate stack, subsequently forming halo/extension regions for the first gate stack, and independently forming halo/extension regions for the second gate stack. Embodiments include forming the eSiGe regions by wet etching the substrate with TMAH using the nitride spacers as a soft mask, forming sigma shaped cavities, and epitaxially growing in situ boron doped eSiGe in the cavities.Type: ApplicationFiled: April 19, 2011Publication date: October 25, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Matthias Kessler, Ricardo Mikalo
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Patent number: 8268689Abstract: A method for fabricating a field effect transistor device includes forming a first conducting channel and a second conducting channel, forming a first gate stack on the first conducting channel to partially define a first device, forming second gate stack on the second conducting channel to partially define a second device, implanting ions to form a source region and a drain region connected to the first conducting channel and the second conducting channel, forming a masking layer over second device, a portion of the source region and a portion of the drain region, performing a first annealing process operative to change a threshold voltage of the first device, removing a portion of the masking layer to expose the second device, and performing a second annealing process operative to change the threshold voltage of the first device and a threshold voltage of the second device.Type: GrantFiled: August 23, 2010Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Dechao Guo, Keith Kwong Hon Wong
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Patent number: 8232186Abstract: Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.Type: GrantFiled: May 29, 2008Date of Patent: July 31, 2012Assignees: International Business Machines Corporation, GlobalfoundriesInventors: Eric C. T. Harley, Judson R. Holt, Dominic J. Schepis, Michael D. Steigerwalt, Linda Black, Rick Carter
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Publication number: 20120190159Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.Type: ApplicationFiled: March 26, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Jeffrey W. Sleight
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Patent number: 8227316Abstract: A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.Type: GrantFiled: June 29, 2006Date of Patent: July 24, 2012Assignee: International Business Machines CorporationInventors: Huilong Zhu, Oleg Gluschenkov, Jing Wang
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Patent number: 8216903Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: GrantFiled: September 29, 2005Date of Patent: July 10, 2012
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Publication number: 20120171825Abstract: In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.Type: ApplicationFiled: March 6, 2012Publication date: July 5, 2012Inventors: Fujio Masuoka, Keon Jae LEE
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Patent number: 8211773Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: GrantFiled: July 28, 2009Date of Patent: July 3, 2012
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Patent number: 8173497Abstract: A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and a silicon layer. An epi-silicon layer is formed in the buried insulation layer of the peripheral region and connects a peripheral portion of a channel area of the silicon layer to the silicon substrate. A gate is formed on the silicon layer and junction areas are formed in the silicon layer on both sides of the gate.Type: GrantFiled: December 12, 2008Date of Patent: May 8, 2012Assignee: Hynix Semiconductor Inc.Inventor: Ki Bong Nam
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Publication number: 20120080722Abstract: A semiconductor device includes: a semiconductor substrate; a SiGe relaxed layer on the semiconductor substrate; an NMOS transistor on the SiGe relaxed layer; and a PMOS transistor on the SiGe relaxed layer, in which the NMOS transistor includes a tensile strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer; and the PMOS transistor includes a compressive strained epitaxial layer located on the SiGe relaxed layer or embedded in the SiGe relaxed layer. The loss of the strained semiconductor material can be avoided and meanwhile the stress in the channel can be better maintained.Type: ApplicationFiled: February 25, 2011Publication date: April 5, 2012Applicant: Institute of Microelectronics,Chinese Academy of SciencesInventors: Haizhou Yin, Zhijiong Luo, Huilong Zhu
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Patent number: 8148221Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.Type: GrantFiled: October 19, 2009Date of Patent: April 3, 2012Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Khee Yong Lim, Victor Chan, Eng Hua Lim, Wenhe Lin, Jamin F. Fen
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Patent number: 8138544Abstract: A castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device includes a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed in the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascade structure. Trench isolation insulator islands, having upper and lower surfaces, surround the source and drain regions as well as the channel-forming regions. Both the primary and secondary channel-forming regions include pluralities of thin, spaced, vertically-orientated semiconductor channel elements that span longitudinally along the device between the source and drain regions.Type: GrantFiled: February 23, 2010Date of Patent: March 20, 2012Inventor: John James Seliskar