With Particular Manufacturing Method Of Gate Sidewall Spacers, E.g., Double Spacers, Particular Spacer Material Or Shape (epo) Patents (Class 257/E21.64)
  • Patent number: 7091549
    Abstract: The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: August 15, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul J. Rudeck, Graham Wolstenholme, Robert Carr
  • Patent number: 7078287
    Abstract: A gate electrode is formed on a silicon substrate. First spacers are formed on side surfaces of the gate electrode. With the gate electrode and the first spacers as masks, the surface of the silicon substrate is chipped off to form steplike portions at positions adjacent to base portions of the first spacers. Second spacers are formed at the steplike portions. Silicides are formed on the silicon substrate with the first spacers and the second spacers as masks.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: July 18, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroshi Nagatomo
  • Patent number: 6794764
    Abstract: The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the bitline contacts to prevent damage caused during the formation of the bitline contacts. The present invention also relates to a method of forming the memory array.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: September 21, 2004
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Tazrien Kamal, Mark T. Ramsbey, Hidehiko Shiraiwa, Fred T K Cheung