Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

Abstract: An integrated circuit has at least one semiconductor device for storing charge that includes at least one elementary active component and at least one elementary storage capacitor. The device includes a substrate having a lower region containing at least one buried capacitive elementary trench forming the elementary storage capacitor, and an elementary well located above the lower region of the substrate and isolated laterally by a lateral electrical isolation region. The elementary active component is located in the elementary well or in and on the elementary well. The capacitive elementary trench is located under the elementary active component and is in electrical contact with the elementary well. In one preferred embodiment, the lateral electrical isolation region is formed by a trench filled with a dielectric material and has a greater depth than that of the elementary well. Also provided is a method for fabricating an integrated circuit that includes a semiconductor device for storing charge.

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract: A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.

Abstract: A process for fabricating a dynamic random access memory is provided. In this fabrication process, the steps of forming the silicon layer, and performing the ion implantation process and the removing process are repeated at least twice and the oxidation process is performed once to form an oxidation spacer that is larger than the landing area for a bit line contact in the prior art. Therefore, when defining a bit line contact opening, a larger process window is fabricated to prevent the occurrence of a short between the bit line contact and the gate of a transistor due to misalignment.

Abstract: Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to form the gate electrode. Hence the resulting devices have a reduced area for the cell array. The semiconductor memory device is composed of a substrate having trenches formed side by side, a plate electrode which is formed to a prescribed depth from the surface of the inner wall of the trench, a capacitor insulating film which covers the surface of the inner wall of the trench, a memory node electrode MN which fills the trench, with the capacitor insulating film interposed between them, and a memory node contact plug which is buried in a contact hole which is so made as to reach the memory node electrode from the surface of the semiconductor layer.

Abstract: Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

Abstract: A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the <100> and <110> directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract: A method for fabricating a semiconductor device having a capacitor is provided. The method includes forming an isolation layer on a substrate on which a capacitor region and a transistor region are defined, forming a trench in the isolation layer, sequentially forming a first polysilicon layer, a dielectric layer, and a second polysilicon layer on an entire surface of the substrate including the trench, forming a capacitor in the trench by performing a chemical mechanical polishing process until an upper surface of the isolation layer is exposed, forming a first photoresist pattern to expose the transistor region, removing the second polysilicon layer and the dielectric layer using the first photoresist pattern as a mask, forming a second photoresist pattern in the transistor region, and forming a gate electrode by selectively removing the first polysilicon layer in the transistor region using the second photoresist pattern as a mask.

Abstract: The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.

Abstract: A stacked capacitor formed in a capacitor hole includes a bottom electrode, capacitor insulation film and a top electrode. The bottom electrode includes a plurality of islands formed on an underlying insulating film, and a metallic film covering the islands on the underlying insulating film. The larger surface of the bottom electrode increases the capacitance of the stacked capacitor.

Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: The invention relates to a trench capacitor, in particular for use in a semiconductor memory cell, comprising a trench (2), embodied in a substrate (1), a first region (1a), provided in the substrate (1), as first capacitor electrode, a dielectric layer (10) on the trench wall as capacitor dielectric and a metallic filler material (30?) provided in the trench (2) as second electrode. Above the conducting metallic filling material (30?) a dielectric filling material (35) is provided in the trench (2) with a cavity (40) provided for mechanical tensions. The invention further relates to a corresponding method of production.

Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming a sacrificial layer over the substrate and filling the first trench, etching the sacrificial layer to have a portion of the sacrificial layer remain in the first trench in the BLC region of the substrate, forming a second trench extending horizontally by etching the substrate underneath the first trench, and filling the first and second trenches to form an isolation structure.

Abstract: A semiconductor memory device and fabrication method thereof. In a semiconductor memory device, each memory cell comprises a deep trench and a capacitor disposed on the lower portion thereof. A collar oxide layer having a first second sidewalls is disposed on the deep trench. The top of the first sidewall is at the same height as the surface of the semiconductor substrate. The top of the second sidewall is substantially equal to the top of the capacitor. The memory cell further comprises a buried conductor layer disposed on the second sidewall and the capacitor and a buried strap adjoining the buried conductive layer, and a transistor disposed on the surface of the semiconductor substrate and electrically connected to the capacitor through the buried strap and the buried conductive layer.

Abstract: A capacitor device includes a substrate, a first conductive structure, a second conductive structure, a dielectric layer structure, and a recess in the substrate. The first and second conductive structures are disposed on opposite sides of the dielectric layer structure, and the dielectric layer structure extends in a meander-shaped manner in a cross-section through the recess.

Abstract: The present invention provides a fabrication method for a trench capacitor having an insulation collar (10) in a silicon substrate (1), having the steps of: providing a trench (5) in the silicon substrate (1); providing the insulation collar (10) in the upper trench region as far as the top side of the silicon substrate (1); depositing a layer (12) made of a metal oxide in the trench (5); carrying out a thermal treatment for selectively reducing the layer (12), a region of the layer (12) that lies below the insulation collar (10) above the silicon substrate (1) being reduced and being converted into a first capacitor electrode layer (15) made of a corresponding metal silicide, and a region of the layer (12) that lies above the insulation collar (10) not being reduced; selectively removing the non-reduced region of the layer (12) that lies above the insulation collar (10); providing a capacitor dielectric layer (18) in the trench (5) above the first capacitor electrode layer (15); and providing a second capaci

Abstract: The present invention relates to a manufacturing method for a trench capacitor having an isolation collar which is electrically connected with a substrate on a single side via a buried contact. More specifically, the present invention relates to manufacturing method for a trench capacitor having an isolation collar with a metal conductive fill in the collar region connected to a metal fill in the capacitor region.

Abstract: A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory cells are arranged in cell rows offset with respect to one another and are separated from one another by strip-like isolator structures. Buried word lines are embedded in the isolator structures and run along the longitudinal faces of semiconductor fins which are formed along the cell rows and include the active regions of the selection transistors. The internal electrodes of the trench capacitors are each connected with a low impedance via surface straps to first source/drain areas of the respective selection transistors. In one embodiment, one word line is formed for each isolator structure using an open bit line architecture, with only every alternate word line being used for addressing. A reinforced word line/trench isolator is provided between the word lines and the trench capacitors.

Abstract: A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack, which if not addressed can cause device failure.

Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.

Abstract: A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.

Abstract: The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.

Abstract: A method of manufacturing dynamic random access memory (DRAM) cylindrical capacitor is provided. A substrate having a polysilicon plug formed therein is provided. A dielectric layer having an opening is disposed on the substrate, wherein the opening exposes the polysilicon plug. Thereafter, an amorphous silicon spacer is formed on the sidewall of the opening to expose a portion of the polysilicon plug. Next, a top portion of the exposed polysilicon plug is removed and a seeding method is used to grow a hemispherical silicon grain (HSG) layer on a surface of the amorphous silicon spacer. A capacitor dielectric layer is formed on the surface of the HSG layer and a conductive layer is then formed on the capacitor dielectric layer. As no HSG is formed on the polysilicon plug, and therefore the contact area of the capacitor is not decreased.

Abstract: Methods of forming a deep trench capacitor memory device and logic devices on a single chip with hybrid surface orientation. The methods allow for fabrication of a system-on-chip (SoC) with enhanced performance including n-type complementary metal oxide semiconductor (CMOS) device SOI arrays and logic transistors on (100) surface orientation silicon, and p-type CMOS logic transistors on (110) surface orientation silicon. In addition, the method fabricates a silicon substrate trench capacitor within a hybrid surface orientation SOI and bulk substrate. Cost-savings is realized in that the array mask open and patterning for silicon epitaxial growth is accomplished in the same step and with the same mask.

Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.

Abstract: Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

Abstract: A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

Abstract: A trench capacitor with improved strap is disclosed. The strap is located above the top surface of the capacitor. The top surface of the trench capacitor, which is formed by the top surfaces of the collar and storage plate, is planar. By locating the strap on a planar surface, the divot present in conventional strap processes is avoided. This results in improved strap reliability and device performance.

Abstract: The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).

Abstract: A semiconductor device and a method for fabricating the same. The device comprises a silicon substrate having a conductive well; a trench formed in the conductive well; a plate electrode formed on the sidewall of the trench; a capacitor insulating film and a storage node electrode; a first storage node connector formed on the storage node electrode; an insulating film formed on the first storage node connector; a silicon layer formed on the entire structure; word lines formed on the silicon layer; source and drain regions formed in the silicon layer; a contact hole, formed in the silicon layer and the insulating film, such that the first storage node connector and the source region are exposed; and a second storage node connector, formed in the contact hole, such that the source region and the first storage node connector are connected to each other.

Abstract: A method for fabricating a deep trench capacitor of DRAM devices is disclosed. A substrate with a deep trench formed therein is provided. The trench is then doped to form a buried plate electrode serving as a first electrode of the deep trench capacitor at a lower portion of the deep trench. An isolation dielectric film is formed on interior surface of the deep trench. Subsequently, a first polysilicon layer is deposited on the isolation dielectric film to fill the deep trench. The first polysilicon layer is recessed to a first depth d1 under the surface of the substrate. A thin silicon film is deposited on the recessed first polysilicon layer and also on the exposed isolation dielectric film. A anisotropic etching is carried out to etch the thin silicon film, the subjacent recessed first polysilicon layer to a second depth d2 under the surface of the substrate. The remaining silicon film becomes a silicon spacer protecting the upper portion of the isolation dielectric film.

Abstract: Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed.