Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.

Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

Abstract: The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

Abstract: A memory cell and array and a method of forming a memory cell and array are disclosed. An embodiment is a memory cell comprising first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

Abstract: Methods and apparatus for providing finFET SRAM cells. An SRAM cell structure is provided including a central N-well region and a first and a second P-well region on opposing sides of the central N-well region, having an area ratio of the N-well region to the P-well regions between 80-120%, the SRAM cell structure further includes at least one p-type transistor formed in the N-well region and having a gate electrode comprising a gate and a gate dielectric over a p-type transistor active area in the N-well region; and at least one n-type transistor formed in each of the first and second P-well regions and each n-type transistor having a gate electrode comprising a gate and a gate dielectric over an n-type transistor active area in the respective P-well region. Methods for operating the SRAM cell structures are disclosed.

Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

Abstract: A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.

Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.

Abstract: According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active regions and prevent IDD failure because a gate pattern is formed on a guard region provided at a periphery of the cell region.

Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Abstract: Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

Abstract: Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.

Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.

Abstract: According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less.

Abstract: An enhanced shallow trench isolation method for fabricating radiation tolerant integrated circuit devices is disclosed. A layer of pad oxide is first deposited on a semiconductor substrate. A layer of pad nitride is then deposited on the pad oxide layer. A trench is defined within the semiconductor substrate by selectively etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate. Boron ions are then implanted into both the bottom and along the sidewalls of the trench. Subsequently, a trench plug is formed within the trench by depositing an insulating material into the trench and by removing an excess portion of the insulating material. A p-well is implanted to a depth just below the depth of the bottom of the trench. This helps to keep the threshold voltage of the IC device below the trench at a high level, and thereby keep post-radiation leakage low. Then, an electrically neutral species is implanted into the wafer.

Abstract: A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element.

Abstract: It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.

Abstract: An electronic device (100), comprises a first electrode (101), a second electrode (102) and a convertible structure (103) connected between the first electrode (101) and the second electrode (102), which convertible structure (103) is convertible between at least two states by heating, wherein the convertible structure (103) has different electrical properties in different ones of the at least two states, wherein the convertible structure (103) is curved in a manner to increase a length of a path of an electric current propagating through the convertible structure (103) between the first electrode (101) and the second electrode (102).

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more.

Abstract: A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer.

Abstract: An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

Abstract: A method for fabricating a microelectronic device with one or several asymmetric and symmetric double-gate transistors on the same substrate.

Abstract: A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

Abstract: A CMOS inverter formed with narrowly spaced fins structures including transistors formed on sidewalls of each fin structure. A high-k dielectric material is deposited on the fins to provide mechanical stability to the fins and serve as a gate dielectric material. A mid gap metal gate layer may be formed on the high-k dielectric layer.

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Abstract: A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.

Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) first and second semiconductor body regions. The method further includes forming (i) a gate divider region and (ii) a gate electrode layer on top of the semiconductor substrate. The gate divider region is in direct physical contact with gate electrode layer. A top surface of the gate electrode layer and a top surface of the gate divider region are essentially coplanar. The method further includes patterning the gate electrode layer resulting in a first gate electrode region and a second gate electrode region. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Abstract: The present invention provides a semiconductor device including SRAM cell units each including a data holding section made up of a pair of driving transistors and a pair of load transistors, a data write section made up of a pair of access transistors, and a data read section made up of an access transistor and a driving transistor, wherein each of the transistors includes a semiconductor layer projecting upward from a base plane, a gate electrode extending from a top to opposite side surfaces of the semiconductor layer so as to stride the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and source/drain areas, a longitudinal direction of each of the semiconductor layers is provided along a first direction, and for all the corresponding transistors between the SRAM cell units adjacent to each other in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer along the first dire

Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.

Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract: A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.

Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.

Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.

Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.

Abstract: A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.