Abstract: Disclosed is a complementary CMOS device having a first FET with sidewall channels and a second FET with a planar channel. The first FET can be a p-FET and the second FET can be an n-FET or vice versa. The conductor used to form the gate electrodes of the different type FETs is different and is pre-selected to optimize performance. For example, a p-FET gate electrode material can have a work function near the valence band and an n-FET gate electrode material can have a work function near the conduction band. The first gate electrodes of the first FET are located adjacent to the sidewall channels and the second gate electrode of the second FET is located above the planar channel. However, the device structure is unique in that the second gate electrode extends laterally above the first FET and is electrically coupled to the first gate electrodes.

Abstract: A display substrate that has increased aperture ratio is presented. The display substrate includes a base substrate, a first metal pattern formed on the base substrate and a gate wiring and a gate electrode. A first insulating layer is formed on the base substrate covering the first metal pattern. A second metal pattern is formed on the first insulating layer including a data wiring crossing the gate wiring, a source electrode connected to the data wiring and a drain electrode separated from the source electrode. A second insulating layer is formed on the base substrate covering the second metal pattern. A transparent electrode is formed on the second insulating layer. An organic layer is formed on the transparent electrode, and a pixel electrode is formed on the organic layer being insulated with the transparent electrode, and contacted to the drain electrode. The organic layer may comprise red, green and blue color filters.

Abstract: The present invention provides a semiconductor memory device comprising a semiconductor substrate formed of a support substrate, an insulating film formed over the support substrate and a semiconductor layer formed over the insulating film; a MOSFET having a source layer and a drain layer both formed in the semiconductor layer of a transistor forming area set to the semiconductor substrate, and a channel region provided between the source and drain layers; a MOS capacitor having a capacitor electrode which is formed in the semiconductor layer of a capacitor forming area set to the semiconductor substrate and in which an impurity of the same type as the source layer is diffused; and a device isolation layer which insulates and separates between the semiconductor layer formed with the MOSFET and the semiconductor layer formed with the MOS capacitor, wherein the capacitor electrode of the MOS capacitor is formed in polygon and slanting faces enlarged toward the insulating film are provided therearound, and where

Abstract: A PIN diode-based monolithic Nuclear Event Detector and method of manufacturing same for use in detecting a desired level of gamma radiation, in which a PIN diode is integrated with signal processing circuitry, for example CMOS circuitry, in a single thin-film Silicon On Insulator (SOI) chip. The PIN diode is implemented in the p- substrate layer. The signal processing circuitry is located in a thin semiconductor layer and is in electrical communication with the PIN diode. The PIN diode may be integrated with the signal processing circuitry onto a single chip, or may be fabricated stand alone using SOI methods according to the method of the invention.

Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.

Abstract: To provide a low-cost high performance semiconductor device and a method for manufacturing the semiconductor device, a separate single-crystal semiconductor layer having a first region and a non-single-crystal semiconductor layer having a second region are provided over a substrate. Further, it is preferable that a cap film is formed over either the separate single-crystal semiconductor layer or the non-single-crystal semiconductor layer, and the first region and the second region are irradiated with a laser beam by applying the laser beam from above the cap film.

Abstract: Disclosed is a liquid crystal display device having a signal line of low electrical resistivity and high adhesion with an underlayer, wherein a copper alloy film is formed on an underlayer, and an oxide film, silicide film or nitride film, which are additive metal elements of the copper alloy, is formed at the boundary between the underlayer and the copper alloy film whereby the signal line is formed with a multi-layer film of the copper alloy film and the oxide film, the silicide film, or the nitride film.

Abstract: To reduce variation among TFTs in manufacture of a semiconductor device including n-type thin film transistors and p-type thin film transistors. Further, another object of the present invention is to reduce the number of masks and manufacturing steps, and manufacturing time. A method of manufacturing a semiconductor device includes forming an island-shaped semiconductor layer of a first thin film transistor, then, forming an island-shaped semiconductor layer of the second thin film transistor. In the formation of the island-shaped semiconductor layer of the second thin film transistor, a gate insulating film in contact with the island-shaped semiconductor layer of the second thin film transistor is used as a protection film (an etching stopper film) for the island-shaped semiconductor layer of the first thin film transistor.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.

Abstract: This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of a opening penetrating through the semiconductor layer; a first gate electrode penetrating through the opening and isolated from the semiconductor layer by the first gate dielectric film; a second gate dielectric film formed on a side surface and an upper surface of the semiconductor layer located on the first gate electrode; and a second gate electrode provided on the side surface and the upper surface of the semiconductor layer via the second gate dielectric film, isolated from the first gate electrode, and superimposed on the first gate electrode.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A method for manufacturing a semiconductor substrate is provided, which comprises a step of irradiating a single crystal semiconductor substrate with ions to form an embrittlement layer in the single crystal semiconductor substrate, a step of forming a silicon oxide film over the single crystal semiconductor substrate, a step of bonding the single crystal semiconductor substrate and a substrate having an insulating surface with the silicon oxide film interposed therebetween, a step of performing a thermal treatment, and a step of separating the single crystal semiconductor substrate with a single crystal semiconductor layer left over the substrate having the insulating surface.

Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

Abstract: A liquid crystal display device with a sensing function and a method of fabricating the same are disclosed. The device comprising gate and data lines crossing each other on a substrate, so as to define a pixel region including a pixel electrode; a first switching thin film transistor disposed at a crossing of the gate and data lines; a sensing thin film transistor, disposed at a predetermined portion of the pixel region, that senses external light; a sensing storage capacitor that stores a signal sensed by the sensing thin film transistor; and a second switching thin film transistor that receives the sensing signal stored and reads information that is externally inputted, wherein the sensing storage capacitor and the second switching thin film transistor are provided with a reflective region including a reflective electrode.

Abstract: It is an object of the present invention to manufacture a semiconductor element and an integrated circuit that have high performance over a large-sized substrate with high throughput and high productivity. When single crystal semiconductor layers are transferred from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers divided such that they have the size of semiconductor elements to be manufactured are transferred to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate.

Abstract: Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

Abstract: A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.

Abstract: An objective of this invention is to solve the problem caused by a difference in a silicon layer film thickness between a memory cell region and a region other than the memory cell region. For solving the problem, while maintaining a structure where an MOS type transistor in a memory cell region is in a floating state and an MOS type transistor in the region other than the memory cell region is not in a floating state, a film thickness of semiconductor layers having a body regions is made equal in these MOS type transistors.

Abstract: A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.

Abstract: Five photomasks are used in fabricating the pixel structure of an LCD. In this pixel structure, a metal light-shielding layer is formed under the thin film transistor to reduce photocurrent. Furthermore, a metal conductive wire is used to increase the storage capacity of the storage capacitor.

Abstract: A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a <110> direction. These wafers are surface-bonded together so that the <110>directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in <110> direction to the upper wafer, and the other of which is equal in <110> direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.

Abstract: A method for fabricating a semiconductor structure with a multi-layer storage capacitor is provided. A substrate having an active element area and a storage capacitor area is provided. By sequentially fabricating a semiconductor layer, a first inter-layer dielectric (ILD) layer, a gate and a first electrode, a source and a drain in the semiconductor layer in the active element area, a second ILD layer, a patterned conductive layer served as a pixel electrode, a patterned third ILD layer, a plurality of contact windows in the first, second and third ILD layers for exposing the source, the drain, parts of the patterned conductive layer and the first electrode, a second electrode and a source/drain conductive line, the semiconductor structure with the multi-layer storage is obtained in consequence.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A manufacturing method of a thin film transistor is provided. A buffer layer is formed on a substrate, and then a first and a second poly-silicon island are formed thereon. A gate-insulating layer is formed on the substrate, and a first and a second gate are formed thereon. A sacrificed layer is formed on the substrate and a photo-resist layer is formed thereon. The sacrificed layer above the first poly-silicon island is removed by using the photo-resist layer as a mask. A first ion implantation process is performed to form a first source/drain. The photo-resist layer is removed and a second ion implantation process is performed to form a second source/drain. At the same time, the second ion implantation process is used to implant ions into the buffer layer below the two sides of the second gate. A lightly-doped ion implantation process is performed after removing the sacrificed layer.

Abstract: The method comprises steps consisting of: forming, on an isolating face of a first substrate, a stack comprising successively at least one layer of rear grid material, an electrically insulating rear grid layer, a semi-conducting zone, an electrically insulating layer for the front grid, at least one layer of front grid material and a masking element, placed facing the semi-conducting zone, forming in the layer of front grid material a pattern reproducing the shape of the masking element and comprising etching of the layer of front grid material to eliminate the front grid material outside said pattern, forming on the free faces of the pattern a sacrificial spacer covering a first part of the semi-conducting zone revealed by eliminating the grid material, forming a protective layer over the remaining part, or second part, of the semi-conducting zone revealed by eliminating the grid material, eliminating the sacrificial spacer covering said first part of the semi-conducting zone, etching the first part of t

Abstract: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

Abstract: An array substrate includes a base substrate, a plurality of gate lines, a plurality of data lines, a plurality of pixel portions and a gate driving section. The base substrate includes a display area, a boundary area surrounding the display area and a light-blocking area surrounding the boundary area. The gate lines extend in a first direction on the base substrate. The data lines extend in a second direction crossing the first direction on the base substrate. The pixel portions are disposed in the display area and electrically connected to the gate and data lines. The gate driving section is electrically connected to the gate lines. A portion of the gate driving section overlaps the boundary area. The gate driving section overlaps the boundary area.

Abstract: A method for manufacturing a substrate for a flat panel display device is disclosed. The present method uses photolithography with four masks to manufacture a TFT-LCD. After the third half-tone mask is used, the manufacturing of the TFTs and the defining of the pixel area of the substrate can be completed. The present method can avoid the alignment deviation and the generation of parasitic capacitance happened on the substrate made through the conventional photolithography with five masks. Therefore, the present method can reduce the costs and increase the yield. Moreover, the substrate for the TFT-LCD made by the present method can define a channel region in the semiconductor layer after the second half-tone mask. Hence, the subsequent manufacturing for forming a transparent conductive layer, a source, and a drain can be achieved by wet etching to effectively reduce the non-homogeneous etching for the channel region in the semiconductor layer.

Abstract: The invention relates to a thin film transistor substrate and a display device including the same, and provides a thin film transistor substrate and a display device including the same, which can prevent damage of elements due to static electricity by forming, in each unit pixel region where a pair of first and second pixel electrodes, a pair of first and second drain electrode plates that are connected to the first and second pixel electrodes and to connected to drain terminals of thin film transistors, and can obtain a dot inversion driving effect through line inversion driving by connecting the first drain electrode in one pixel region to the first drain electrode plate, connecting the second drain electrode in the one unit pixel region to the second drain electrode plate, connecting a first drain electrode in another unit pixel region neighboring the one unit pixel region to the second drain electrode plate, and connecting a second drain electrode in another unit pixel region to the first drain electrode

Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.

Abstract: In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.

Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

Abstract: A thin film transistor (TFT) substrate and a method of manufacturing the same in which the surface of a data pattern is implanted with ions to increase the adhesion force with a passivation layer formed by a subsequent process. The TFT substrate includes: an active layer having a channel region formed of a semiconductor and source and drain regions doped with impurities; a data pattern formed on the active layer and including source and drain electrodes, the surface of which is implanted with ions to increase hydrophobicity and roughness; a passivation layer formed on the data pattern and including a pixel contact hole exposing a portion of the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the pixel contact hole, and a method of manufacturing the same.

Abstract: A thin film transistor includes first and second ohmic contacts formed on a substrate, wherein each of the first and second ohmic contacts includes polycrystalline silicon; a semiconductor formed on the first and second ohmic contacts and the substrate, the semiconductor including microcrystalline silicon; a blocking member formed on the semiconductor; an input electrode formed on the first ohmic contact; an output electrode formed on the second ohmic contact; an insulating layer formed on the blocking member, the input electrode, and the output electrode; and a control electrode formed on the insulating layer and disposed on the semiconductor.

Abstract: A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Abstract: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region.

Abstract: A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower layers. The upper layer may have a carrier concentration lower than the lower layer. A method of manufacturing a transistor may include: forming a channel layer on a substrate; forming source and drain electrodes on the substrate; forming a gate insulating layer on the substrate; and forming a gate electrode on the gate insulating layer above the channel layer. A method of manufacturing a transistor may include: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a channel layer on the gate insulating layer; and forming source and drain electrodes on the gate insulating layer.

Abstract: A method for manufacturing a thin film transistor substrate includes (a) a step of forming a plurality of island-like semiconductor films (13) above an insulating transparent substrate (10); (b) a step of forming a gate insulating film (21) on each of the island-like semiconductor films (13); (c) a step of forming first conductivity type LDD regions on both sides in the first island-like semiconductor film (13) by leaving a channel region and forming a first conductivity type normally-on channel region having an impurity density equivalent to that of the LDD region in the second island-like semiconductor film (13); (d) a step of forming a first gate electrode (32a) partially covering the LDD region and forming a second gate electrode (33a) above the normally-on channel region, and (e) a step of forming a first conductivity type source/drain region having an impurity density higher than that of the LDD region in regions on the both sides of the gate electrode.

Abstract: A flexible display substrate includes: a thin film transistor on the flexible substrate, the thin film transistor including a gate electrode, a gate insulating layer insulating the gate electrode, a channel layer on the gate insulating layer, a source electrode connected with the channel layer, and a drain electrode connected with the channel layer; a first stress absorbing layer below the thin film transistor; a first protection layer on the first stress absorbing layer; a second stress absorbing layer on the thin film transistor; a second protection layer on the second stress absorbing layer; and a pixel electrode on the second protection layer, the pixel electrode being connected with the drain electrode.

Abstract: Provided is a method of manufacturing a thin film transistor panel that may reduce manufacturing costs. The method includes forming gate wires including a gate line and a gate electrode on an insulating substrate and forming data wires including source and drain electrodes, the data wires being insulated from the gate wires. The method further includes forming a passivation layer covering the gate and data wires, forming contact holes exposing the drain electrodes by etching the passivation layer, and forming a pixel electrode by depositing an indium-free transparent conductive film on the exposed drain electrode and the passivation layer and then dry etching the transparent conductive film.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.

Abstract: A method for manufacturing a semiconductor device, comprises: (a) forming a first semiconductor layer on a semiconductor substrate in a first region and forming a second semiconductor layer on the semiconductor substrate in a second region, a thickness of the first semiconductor layer being larger than a thickness of the second semiconductor layer; (b) forming a third semiconductor layer on the first semiconductor layer and the second semiconductor layer; (c) forming a first cavity between the third semiconductor layer and the semiconductor substrate in the first region, and a second cavity between the third semiconductor layer and the semiconductor substrate in the second region by removing the first semiconductor layer and the second semiconductor layer, the first cavity and the second cavity having an internal height different each other; (d) forming an insulation layer inside the first cavity and the second cavity so that the first cavity remains a third cavity defined by the insulation layer formed both

Abstract: Semiconductor storage devices in which a plurality of semiconductor element devices having different functions are disposed in the appropriate region of the partial SOI substrate and the interface between each gate insulator and each gate electrode is formed to be the same level, and manufacturing methods thereof are disclosed. According to one aspect, there is provided a semiconductor storage device includes a first semiconductor region provided in a semiconductor substrate including a buried insulator having opening portions, a second semiconductor region without including buried insulator, a plurality of first semiconductor element devices disposed above the buried insulator, a plurality of second semiconductor element devices each disposed in a region including a region above the opening portion of the buried insulator, and a plurality of third semiconductor element devices disposed in the second semiconductor region.

Abstract: An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Abstract: A TFT array panel and a manufacturing method thereof, The TFT array panel includes an insulation substrate, a plurality of gate lines, a plurality of first dummy wiring lines, a gate insulating layer, and a plurality of data lines. The insulation substrate has a display area for displaying an image and a peripheral area outside the display area. The plurality of gate lines are formed in the display area and in a portion of the peripheral area. The plurality of first dummy wiring lines are insulated from the gate lines and formed in the peripheral area. The gate insulating later is formed on the gate lines and the first dummy wiring lines, and has at least one contact hole exposing at least lateral end portions of the first dummy wiring lines.

Abstract: MOSFET on SOI device, comprising: an upper region comprising at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first metallic layer and a first portion of a second semi-conductor layer, a lower region comprising at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one metallic portion, the second semi-conductor layer being arranged on a second dielectric layer stacked on a second metallic layer.

Abstract: A method is provided for fabricating a semiconductor-on-insulator (“SOI”) substrate including (i) an SOI layer of monocrystalline silicon separated from (ii) a bulk semiconductor layer by (ii) a buried oxide (“BOX”) layer, the BOX layer including a layer of doped silicate glass. In such method, a sacrificial stressed layer is deposited to overlie the SOI layer and trenches are etched through the sacrificial stressed layer and into the SOI layer. The SOI substrate is heated with the sacrificial stressed layer sufficiently to cause the glass layer to soften, thereby causing the sacrificial stressed layer to apply stress to the SOI layer to form a stressed SOI layer. A dielectric material can then be deposited in the trenches to form isolation regions contacting peripheral edges of the stressed SOI layer, the isolation regions extending from a major surface of the stressed SOI layer towards the BOX layer. The sacrificial stressed layer can then be removed to expose the stressed SOI layer.

Abstract: A display substrate includes a gate line, a data line, a pixel electrode and a source pad part. The gate line is formed on a base substrate. The data line crosses the gate line to define a pixel area. The pixel electrode makes contact with the base substrate. The source pad part is formed on an end portion of the data line, the source pad part including a source metal layer, a conductive etch stop layer formed on the source metal layer and a source pad electrode formed on the conductive etch stop layer. Thus, the conductive etch stop layer of the source pad part prevents the source metal layer of the source pad part from being damaged and the conductive etch stop layer of the source pad part may fully make contact with the source pad electrode.