Abstract: A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: This manufacturing method of a metal component enables precision processing of a corner portion, and the radius of curvature of a cog tip of a gear and the like can be made smaller than before. The manufacturing method of a metal component includes: (a) forming a mask film having, in plan view, a first side, a second side, and an extension portion that extends from a region between the first side and the second side on a metal film; and (b) forming a corner portion having, in plan view, a third side and a fourth side by etching the metal film.

Abstract: In various embodiments, a method for manufacturing a chip arrangement, the method including bonding a microphone chip to a first carrier, the microphone chip including a microphone structure, depositing adhesive material laterally disposed from the microphone structure, and arranging the microphone structure into a cavity of a second carrier such that the adhesive material fixes the microphone chip to the cavity of the second carrier.

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

Abstract: A manufacturing method for a light emitting device can include providing a bonding layer over a base, and disposing a shim plate with an opening over the bonding layer. A light emitting body is disposed over the bonding layer exposed from the opening of the shim plate. A lens is formed by approaching a die having a concave portion at its surface, to the shim plate, covering an upper surface of the light emitting body and an upper surface of the shim plate with a lens formation material within the concave portion, and then hardening the lens formation material.

Abstract: A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.

Abstract: Embodiments of the present invention provide a method of forming carbon nanotube based semiconductor devices. The method includes creating a guiding structure in a substrate for forming a device; dispersing a plurality of carbon nanotubes inside the guiding structure, the plurality of carbon nanotubes having an orientation determined by the guiding structure; fixating the plurality of carbon nanotubes to the guiding structure; and forming one or more contacts to the device. Structure of the formed carbon nanotube device is also provided.

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

Abstract: In various embodiments, a chip module may include a first chip; and a leadframe with a first leadframe area and a second leadframe area, wherein the first leadframe area is electrically insulated from the second leadframe area; wherein the first chip is arranged at least partially on the first leadframe area and at least partially on the second leadframe area.

Abstract: A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring.

Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.

Abstract: The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps.

Abstract: Disclosed is a light emitting device module including a package body, a first lead frame and a second lead frame provided on the package body, a light emitting device electrically connected to the first lead frame and the second lead frame, a first pad and a second pad respectively formed on the lower surfaces of the first lead frame and the second lead frame, and a third pad formed on the lower surface of the package body, wherein at least one of the first pad, the second pad and the third pad includes a plurality of sub-pads.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.

Abstract: A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.

Abstract: A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire.

Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

Abstract: Conventional semiconductor devices have a problem that it is difficult to prevent the short circuit between chips and to improve accuracy in temperature detection with the controlling semiconductor chips. In a semiconductor device of the present invention, a first mount region to which a driving semiconductor chip is fixedly attached and a second mount region to which a controlling semiconductor chip is fixedly attached are formed isolated from each other. A projecting area is formed in the first mount region, and the projecting area protrudes into the second mount region. The controlling semiconductor chip is fixedly attached to the top surfaces of the projecting area and the second mount region by use of an insulating adhesive sheet material. This structure prevents the short circuit between the two chips, and improves accuracy in temperature detection with the controlling semiconductor chip.

Abstract: A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a package body; a plurality of electrodes including a first electrode on the package body; a paste member on the first electrode and including inorganic fillers and metal powder; and a semiconductor device die-bonded on the paste member, wherein a die-bonding region of the first electrode includes a paste groove having a predetermined depth and the paste member is formed in the paste groove.

Abstract: A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.

Abstract: The problem of the present invention is to provide a chip-on-chip type semiconductor electronic component and a semiconductor device which can meet the requirements for further density increase of semiconductor integrated circuits. The present invention provides: a chip-on-chip type semiconductor electronic component in which a circuit surface of a first semiconductor chip and a circuit surface of a second semiconductor chip are opposed to each other, wherein the distance X between the first semiconductor chip and the second semiconductor chip is 50 ?m or less, and the shortest distance Y between the side surface of the second semiconductor chip and the first external electrode is 1 mm or less; and a semiconductor device comprising the same.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: Disclosed is a semiconductor package utilizing a tape to reinforce fixing of leads to a die pad having a through hole. The package primarily comprises a leadframe having the plurality of leads and the die pad, a tape, at least a chip, and an encapsulant. The die pad. The tape is attached beneath the leadframe adjacent to the inner fingers of the leads to fix the leads and the die pad for wire-bonding. Additionally, the tape does not completely cover the through hole. The chip is disposed on the leads and the die pad and electrically connected to the inner fingers. The encapsulant encapsulates the die pad, the tape and the chip with the leads being insulatedly bonded where the encapsulant further completely fills into the through hole through its opening without completely covered by the tape.

Abstract: According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

Abstract: A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side.

Abstract: The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.

Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.

Abstract: A semiconductor device includes a die pad, the die pad including a first surface and a second surface, a first chip arranged on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged on the first surface, a plurality of first recesses formed on the first surface, a plurality of second recesses formed on the first surface, the plurality of second recesses being different from the first plurality of recesses in at least one of size and geometry, a wire, a resin, and a lead, one end of the lead being connected to another end of the wire and a part the lead being encapsulated by the resin. The plurality of first recesses includes a third recess and a fourth recess, and the first chip is arranged in a first area.

Abstract: A resin-sealed semiconductor device includes a power element (1), a control element (4), a first lead frame (3) having a first die pad (3A) which holds the power element (1), a second lead frame (5) having a second die pad (5A) which holds the control element (4), and a housing (6) made of a resin material and sealing the power element, the first die pad, the control element, and the second die pad. A lower surface of the second die pad is higher than an upper surface of the first element, and at least part of the first die pad and at least part of the second die pad overlap each other when viewed from the top. One of the first leads and one of the second leads are directly joined together by a joint portion (23) and electrically coupled together in the housing.

Abstract: A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.

Abstract: A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.

Abstract: Apparatus and methods are provided for integrally packaging antennas with semiconductor IC (integrated circuit) chips to provide highly-integrated and high-performance radio/wireless communications systems for millimeter wave applications including, e.g., voice communication, data communication, and radar applications. For example, wireless communication modules are constructed with IC chips having receiver/transmitter/transceiver integrated circuits and planar antennas that are integrally constructed from BEOL (back end of line) metallization structures of the IC chip.

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract: This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

Abstract: An integrated circuit package on package system includes: providing a lead having a wire-bonded die with a bond wire connected thereto; mounting a fan-in interposer over the wire-bonded die and the bond wire; connecting the fan-in interposer to the lead with the bond wires; and encapsulating the wire-bonded die, bond wires, and the fan-in interposer with an encapsulation leaving a portion of the fan-in interposer exposed.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: In a power semiconductor module, a semiconductor device including electrode surfaces for connection on its front side and back side is connected on its back side to a first extraction electrode through soldering; a metal surface of one side of a laminated conductor having a laminated structure in which at least two types of metals are laminated is directly, intermetallically connected to the front side of the semiconductor device; a second extraction electrode is connected to a metal surface of another side of the laminated conductor through soldering; and the laminated conductor includes a plurality of arch-like protrusions and a straight section connecting the arch-like protrusions, the straight section is connected with the front side of the semiconductor device, and the protrusions are connected with the second extraction electrode.

Abstract: In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.

Abstract: Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.

Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

Abstract: An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead.

Abstract: A copper strap for a semiconductor device package having a contact electrically connected to a die electrode, a leg portion electrically connected to a lead frame, a web portion positioned between the contact and the leg portion and connected to the leg portion and a connection region connecting the web portion to the contact. The contact includes a body having a plurality of formations, each of the plurality of formations having a concavity and an opposing convexity positioned to generally face the die electrode.