Abstract: An object of the present invention is to provide a semiconductor device by packaging a plurality of semiconductor chips three-dimensionally in a smaller thickness, with a smaller footprint, at the lower cost without using any other components and through a simpler manufacturing process of the semiconductor device than with the conventional methods. A flip chip packaging structure is formed by directly connecting a first semiconductor chip (101) reduced in thickness by back grinding and a substrate (105) via a bump electrode (102) to a wiring pattern (106). Also, a second semiconductor chip (103) is formed with an electrode (104) that is higher than the sum of the thickness of the first semiconductor chip (101) and the height of the electrode (102), and the electrode (104) is directly connected to the wiring pattern (106) on the substrate (105), whereby the most-compact three-dimensional semiconductor packaged device is produced.

Abstract: A circuit board including a flexible insulating substrate, a plurality of conductive wirings placed in line on the flexible insulating substrate, and bumps provided at end portions of the respective conductive wirings positioned in a region for mounting a semiconductor chip is provided. The circuit board further includes an auxiliary conductive wiring positioned at an outermost corner of the region for mounting the semiconductor chip, being adjacent to and an outside the outermost conductive wiring, and an auxiliary bump formed on the auxiliary conductive wiring in line with the bumps on the conductive wirings.

Abstract: A semiconductor chip package with a lead frame having a plurality of leads formed along four sides of the lead frame and tie bars extending from an edge of each of the four sides, wherein bottom surfaces of the tie bars are recessed, a semiconductor chip which is adhered to the recessed surfaces of the tie bars, connectors which electrically connect a plurality of chip pads formed on an upper surface of the semiconductor chip with the plurality of leads, and an encapsulant which encapsulates the upper surface of the semiconductor chip, the connector and bonding portions of the connector.

Abstract: A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products.

Abstract: Using one or more reference indicators in die attaching an optoelectronic device to a lead during the assembly of an optoelectronic package. One example method of assembling an optoelectronic package includes detecting a reference indicator included in a first component of an optoelectronic package. The method also includes die attaching a second component to the optoelectronic package at a die attach location. The die attach location is substantially aligned with the reference indicator along a line that intersects the reference indicator and is parallel to either an x-axis or a y-axis of an x-y coordinate system associated with the optoelectronic package.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a metal containment wall and a solder terminal, and a connection joint that electrically connects the routing line and the pad. The metal containment wall includes a cavity, and the solder terminal contacts the metal containment wall in the cavity and is spaced from the routing line.

Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

Abstract: A sensor package apparatus and method are disclosed in which a sensor die is provided and based on a substrate. An integrated circuit is generally associated with the sensor die. A leadframe is also provided, which is connected by at least one weld to the integrated circuit and the substrate. The integrated circuit, the leadframe, and the sensor die are configured in a flip-chip arrangement to protect the sensor die and form a sensor package apparatus that provides compact and robust electrical and physical connections thereof. The integrated circuit can be formed from, for example, silicon carbide. A metallization layer can also be formed on the integrated circuit, wherein the integrated circuit is configured upon the substrate of the sensor die. The metallization layer thus adheres to the integrated circuit via the weld(s).

Abstract: A resin-encapsulated semiconductor device includes a semiconductor chip, a plurality of inner leads that are connected to a group of electrodes of the semiconductor chip, respectively, and an encapsulating resin that encapsulates a connection part located between the semiconductor chip and the inner leads. Each of the inner leads includes a protruded portion provided on a surface thereof on an outer side relative to the periphery of the semiconductor chip. The protruded portion protrudes in a thickness direction and is provided with a step portion formed in its side portion. The group of electrodes of the semiconductor chip is connected to surfaces of inner portions of the inner leads located on an inner side relative to their protruded portions, through electroconductive bumps, respectively. The encapsulating resin encapsulates the semiconductor chip and the electroconductive bumps and is formed to expose surfaces of the protruded portions.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: Disclosed is a semiconductor apparatus including: a first molded resin portion; a plate-shaped lead frame closely attached to the first molded resin portion; a second molded resin portion attached facing the first molded resin portion and the lead frame; and one or more elements attached on the lead frame on a side which faces the second molded resin portion, the one or more elements including a semiconductor element, wherein any part of at least one of the elements does not exist in a region composed of an aggregation of line segments, each line segment being formed by any two points on an outer periphery of the plate-shaped lead frame outside the first and second molded resin portions and all of the line segments being contained inside a board of the lead frame.

Abstract: Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed.

Abstract: A stacked die package includes a substrate or interposer board that includes a contact area on a top surface and landing pads surrounding the contact area. Solder pads are disposed on an opposite side of the substrate. The solder pads are electrically connected with the landing pads by inner board wiring. A reconstituted die, which includes a die surrounded by a frame, is mounted over the substrate. A top die is mounted over the reconstituted die. Both the reconstituted die and the top die are electrically connected to the substrate, e.g., by wire bonds.

Abstract: A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing.

Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.

Abstract: A package structure of semiconductor includes a lead frame, at least one chip, a controlling component and a passive component. Wherein, the controlling component and the chip are configured on the die pad of the lead frame, and encapsulating glue is encapsulated the lead frame, the chip and controlling component to form a packaging body. The encapsulating body is formed at least one cavity, and the depth of the cavity is reached to the surface of the die pad of the lead frame. The passive component is electrically connected to the lead frame inside the cavity.

Abstract: A lead frame has a plurality of first inner leads having distal end portions and parallel to each other, and a plurality of second inner leads having distal end portions opposing the distal end portions of the first inner leads, longer than the first inner leads, and parallel to each other. The semiconductor chip has a plurality of bonding pads arranged along one side of an element formation surface, and is mounted on the surfaces of the plurality of second inner leads using an insulating adhesive. The plurality of bonding wires include first bonding wires which electrically connect the distal end portions of the plurality of first inner leads to some of the plurality of bonding pads, and a plurality of second bonding wires which electrically connect the distal end portions of the plurality of second inner leads to the rest of the plurality of bonding pads.

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Abstract: A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.

Abstract: A semiconductor package mainly includes a leadframe and a first semiconductor chip such as an application specific integrated circuit (ASIC) encapsulated in a first package body having a cavity for receiving a second semiconductor chip such as a pressure sensor chip, and a cover disposed over the cavity of the first package body. At least a portion of the first package body is formed between the second semiconductor chip and the die pad such that the second semiconductor chip is directly disposed on the portion of the first package body instead of the die pad.

Abstract: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.

Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.

Abstract: A chip package having a lead frame, a chip, a plurality of bonding wires, and an insulation material is provided. The lead frame comprises a die pad, a plurality of leads, a plurality of signal pads and a plurality of non-signal pads. The signal pads and non-signal pads are underneath the signal leads and non-signal leads respectively. The non-signal pad is directly connected to a non-signal plane in the circuit board through its own vias. The signal pad has a structure which extends toward its adjacent non-signal pads. With the signal pad size enlarged, the capacitance between the non-signal plane in the circuit board and the signal pad is increased. The increased capacitance compensates the inductance induced from the bonding wires and improves the response of the signal propagation path for RF applications.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternatively, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 ?m. Reflow metals may be on the passive chip surface and the second segment surfaces.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

Abstract: A three-dimensional stacked semiconductor package includes first and second chips, first and second adhesives, first and second wire bonds, a lead and an encapsulant. The chips are disposed on opposite sides of the lead, and the wire bonds contact the same side of the lead.

Abstract: A semiconductor including a leadframe having a die attach paddle and a number of leads is provided. The die attach paddle has a recess to provide a number of mold dams around the periphery of the die attach paddle. An integrated circuit is positioned in the recess. Electrical connections between the integrated circuit and the number of leads are made, and an encapsulant is formed over the integrated circuit and around the number of mold dams.

Abstract: A method of connecting a lead frame (12) lead finger (16a) to a bond pad (18a) on an integrated circuit (IC) die (10) includes bonding a first bonding wire (20a) from the lead finger (16a) to an intermediate point (22). A second bonding wire (20b) is bonded from the lead finger (16a) to the bond pad (18a) such that the first bonding wire (20a) supports the second bonding wire (20b).

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: A conductor substrate for mounting a semiconductor element, at least a portion thereof mounting the semiconductor element being sealed with an insulating resin, wherein an uppermost surface layer of the conductor substrate comprises copper or an alloy thereof, and the conductor substrate is partly or entirely covered with a layer of copper oxide containing a hydroxide formed upon the surface treatment of the conductor substrate and a process of producing the conductor substrate as well as a process for the production of a semiconductor device using the conductor substrate.

Abstract: An island-shaped floating conducting region is provided in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, or peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer. The floating conducting region has floating potential and blocks a depletion layer extending from the wire on the nitride film to the substrate. It is therefore possible to prevent leakage of a high frequency signal to the other side through the depletion layer extending from the wire on the substrate to the substrate in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer.

Abstract: A method of producing an electronic device electrically and mechanically couples an integrated circuit to a leadframe to produce an intermediate assembly. At least a portion of the intermediate assembly then is encapsulated with a molten encapsulating material. After it is encapsulated, the method permits the molten encapsulating material to substantially solidify. A method of detecting the orientation of a sensor as mounted to an external object also is disclosed.

Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip. wherein said supporting forms a cantilever over said first metallic contact and the overhanging end of the cantilever is glued to said second metallic contact.

Abstract: A three-dimensional stacked semiconductor package device includes first and second semiconductor package devices and a conductive bond. The first device includes a first insulative housing, a first semiconductor chip and a first lead that is bent outside the first insulative housing. The second device includes a second insulative housing, a second semiconductor chip and a second lead that is flat outside the second insulative housing. The conductive bond contacts and electrically connects the leads.

Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant.

Abstract: A semiconductor chip 23 is mounted on an island section 22 in a lead frame composed of a lead having the island section 22, a ground-bonding lead section 28 and a lead 21a each continuing in sequence, and other lead terminal sections 21b to 21d, and then a grounding electrode 24a and other electrodes 24b to 24d for the semiconductor chip are respectively wire-bonded to the lead 21a and other lead terminals 21b to 21d by gold wires 25a to 25d before being embedded in a resin to form a package 27. The lead with the semiconductor chip 23 mounted thereon is structured so that the ground-bonding lead section 28 continuing to both the lead 21a and the island section 22 are absent on both the sides of the wire-bonding region 28a with respect to the island section 22 in the longitudinal section along the grounded gold wire 25a.

Abstract: A surface-mountable light emitting diode structural element in which an optoelectronic chip is attached to a chip carrier part of a lead frame, is described. The lead frame has a connection part disposed at a distance from the chip carrier part, and which is electrically conductively connected with an electrical contact of the optoelectronic chip. The chip carrier part presents a number of external connections for improved conduction of heat away from the chip. The external connections project from a casing and at a distance from each other.

Abstract: A semiconductor power component using flat conductor technology includes a vertical current path through a semiconductor power chip. The semiconductor power chip includes at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a flat conductor chip island of a flat conductor leadframe and the top side electrode is electrically connected to an internal flat conductor of the flat conductor leadframe via a connecting element. The connecting element includes a bonding strip extending from the top side electrode to the internal flat conductor and further includes, on the top side of the bonding strip, bonding wires extending from the top side electrode to the internal flat conductor.

Abstract: A lead frame for improving molding reliability and a semiconductor package with the lead frame are proposed. At least one embossed structure, such as a metal bump or recessed portion, is formed on a bonding layer of a wire-bonding area of the lead frame. At least one semiconductor chip is electrically connected to the lead frame via bonding wires bonded to the bonding layer. During a molding process for fabricating an encapsulant to encapsulate the chip, the bonding wires and a portion of the lead frame, the embossed structure makes the bonding layer become uneven and thus increases the contact area and adhesion between the bonding layer and the encapsulant, so as to prevent cracks of the bonding wires and improve the electrical performances and molding reliability.

Abstract: The invention relates to a semiconductor device with conductor tracks between a semiconductor chip and a circuit carrier, and to a method for producing the same. The conductor tracks extend from contact areas on the top side of the semiconductor chip to contact pads on the circuit carrier. The conductor tracks include an electrically conductive polymer in the semiconductor device.

Abstract: A semiconductor device is provided having: a board; a metallization pattern formed on the first face of the board; a first layer formed so as to not cover the first portion of the metallization pattern but to cover the second portion; and a semiconductor chip mounted on the first face of the board and electrically connected with the metallization pattern in the first portion. A resin portion is provided between the semiconductor chip and the board and from there onto the first portion of the metallization pattern outside the semiconductor chip so as to not reach a boundary between the first and second portions. A second layer is provided on the second face of the board so as to overlap the boundary of the metallization pattern and not overlap the resin portion.