Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.

Abstract: A semiconductor device according to an embodiment includes a frame; a substrate provided inside the frame; a first semiconductor chip provided on the substrate and including a first upper electrode, a first lower electrode, and a first gate electrode; a first polarity electrode having a plate-like shape with a part being provided inside the frame and including a primary first polarity terminal provided outside the frame in a first direction, and a secondary first polarity terminal provided outside the frame in a second direction opposite to the first direction; and a second polarity electrode having a plate-like shape facing the first polarity electrode with a part being provided inside the frame and including a primary second polarity terminal provided outside the frame in the first direction, and a secondary second polarity terminal provided outside the frame in the second direction.

Abstract: A novel transparent double-sided adhesive sheet for image display device is provided, that, under the constraint of holding down the thickness of the adhesive sheet to 250 ?m or less, can relieve a distortion arising within the adhesive sheet after laminating even if a member has a stepped portion of 50 ?m to 100 ?m in height on the laminating surface. Proposed is a transparent double-sided adhesive sheet for image display device which is used for the purpose of laminating an image display device constitutive member having on a laminating surface a stepped portion of 50 ?m to 100 ?m in height and a flat surface portion, and another image display device constitutive member, wherein a thickness of the maximum thickness portion of the adhesive sheet is 250 ?m or less, and a gel fraction (a) at a position in contact with a stepped portion after laminating is 10% or greater and smaller than a gel fraction (b) at a position in contact with a flat surface portion.

Abstract: Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.

Abstract: A semiconductor module arrangement includes a semiconductor module having a top side, an underside opposite the top side, and a plurality of electrical connection contacts formed at the top side. The semiconductor module arrangement additionally includes a printed circuit board, a heat sink having a mounting side, and one or a plurality of fixing elements for fixing the printed circuit board to the heat sink. Either a multiplicity of projections are formed at the underside of the semiconductor module and a multiplicity of receiving regions for receiving the projections are formed at the mounting side of the heat sink, or a multiplicity of projections are formed at the mounting side of the heat sink and a multiplicity of receiving regions for receiving the projections are formed at the underside of the semiconductor module. In any case, each of the projections extends into one of the receiving regions.

Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.

Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.

Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

Abstract: The invention relates to an electronic module and to a method for producing same, comprising a mold body (2), a first circuit carrier (3; 13) having a first inner face (3a; 13a), on which electronic components (5) are arranged, and a first outer face (3b; 13b), a second circuit carrier (4; 14) having a second inner face (4a; 14a), on which electronic components (5) are arranged, and a second outer face (4b; 14b), and at least one spring device (6, 7; 16) which connects the inner faces (3a, 14a; 13a, 14a), or surfaces of electronic components (5) arranged thereon, of the first and second circuit carriers (3, 4; 13, 14), wherein the first and second outer faces (3a, 4a; 13a, 14a) are exposed towards the outside of the electronic module in order to emit heat directly to the outside, and wherein the first and second outer faces (3a, 4a; 13a, 14a) are parallel to each other.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract: A device includes a first and second transistors integrated in first and second chips. Each chip has opposed rear and front surfaces, and further has a first conduction terminal and a control terminal on the front surface and a second conduction terminal on the rear surface. The first and second transistors are electrically connected in series by having the first conduction terminals of the first and second transistors be electrically connected. The device includes a common package enclosing the first and second chips, the common package having an insulating body with a mounting surface. A heat sink is also enclosed within the insulating body, the heat sink making electrical contact with the first conduction terminals of the first and second chips on the respective front surfaces, so that the first conduction terminals are electrically connected together through the heat sink.

Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.

Abstract: A substrate structure has a first surface and a second surface. A plurality of carrying members are formed on the first surface and a plurality of conductive traces are formed on the second surface. In addition, the substrate structure has a first, a second and a third thermal stress relief structures. The first thermal stress relief structure is that lengths of the substrate structure in different axial directions are substantially equal to each other. The second thermal stress relief structure is that a plurality of separated alignment marks are formed on the substrate structure. The third thermal stress relief structure is that the substrate structure has at least one clearance area extending along one of the axial directions of the substrate structure and the clearance area has no carrying members and no conductive traces formed thereon.

Abstract: A semiconductor device according to the present invention includes: a power semiconductor element that is a semiconductor element; bonding parts provided for bonding of an upper surface and a lower surface of the semiconductor element; and metal plates bonded to the power semiconductor element from above and below through the bonding parts, wherein the bonding part includes a mesh metal body disposed between the semiconductor element and the metal plate, and a bonding member in which the mesh metal body is embedded.

Abstract: A semiconductor device has a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, and a plurality of heat sink plates embedded in the encapsulating body so as to have a surface that is exposed to an exterior of the encapsulating body and positioned on the same plane. The heat sink plates are spaced from each other.

Abstract: One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

Abstract: An electronic device includes at least one electronic component chip having a first conduction terminal and a control terminal on a first surface of the chip and a second conduction terminal on a second surface opposite the first surface of the chip. An insulating body embeds the chip. The insulating body includes a mounting surface and an electrically conductive heat-sink connected to the first conduction terminal on the first surface of the chip, but insulated from the control terminal. An opening in a first surface of the insulating body exposes a surface of the electrically conductive heat sink. The electrically conductive heat sink includes a perimeter cavity configured for alignment with an encircling configuration of the control terminal, wherein the perimeter cavity contains a material that insulates the control terminal from the heat sink.

Abstract: In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.

Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: In order to prevent an increase in temperature of a discharge resistance discharging an electric charge accumulated in a smoothing capacitor, the present description discloses a power module. The power module has a first lead frame, a second lead frame, first and second semiconductor switches connected in series between the first lead frame and the second lead frame, a resistor connected between the first lead frame and the second lead frame, and a resin package that encapsulates the first lead frame, the second lead frame, the first semiconductor switch, the second semiconductor switch, and the resistor. In this power module, a radiator portion for radiating heat from the first lead frame and/or the second lead frame is formed in at least a part of the package.

Abstract: An electric device with an insulating substrate consisting of an insulating layer and at least one metallization on a surface side of the insulating layer, the metallization being structured and having an electric component on the metallization. The metallization has a layer thickness that is stepped and is greater in an area adjoining the component.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.

Abstract: Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.

Abstract: In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.

Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (QFN) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material. The peripherally positioned leads are attached to a first surface of the heat spreader, and the die is attached to the first surface of the heat spreader within a ring formed by the leads. The encapsulating material encapsulates the die on the heat spreader, encapsulates bond wires, and fills a space between the leads. A second surface of the heat spreader is exposed from the package. End portions of the leads have surfaces that are flush with a surface of the package opposite the second surface of the heat spreader, and that are used as lands for the package.

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract: A semiconductor device according to the present disclosure includes: a plate (13) having a through hole (15); a metal column (16) fixed to the through hole with an insulating member (17) interposed therebetween, and having a projection projecting from the upper surface of the plate; a semiconductor element (12) fixed to the projection; a lead frame (11) electrically connected to the semiconductor element; and a package (14) covering the semiconductor element, and also covering at least part of each of the plate, the metal column, and the lead frame. The lower surface (13b) of the plate is exposed from the package.

Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.

Abstract: According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Abstract: A packaged integrated device can include a die attach pad having a top surface and a bottom surface. A plurality of leads physically and electrically separated from the die attach pad can be positioned at least partially around the perimeter of the die attach pad. An integrated device die can be mounted on the top surface of the die attach pad. A package body can cover the integrated device die and at least part of the plurality of leads, and at least a portion of the bottom surface of each of the plurality of leads can be exposed through the package body. A plating layer can cover substantially the entire width of an etched lower portion of the outer end of each lead and at least the exposed portion of the bottom surface of each lead.

Abstract: In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

Abstract: A purpose of the application is to provide a semiconductor device production method capable of reducing complexity of production operations and keeping production costs low, and enhancing reliability, and a semiconductor device. One aspect of the invention provides a method of producing a semiconductor device, the method including a first bonding step of bonding a first electrode plate and a semiconductor device portion, and a second bonding step of bonding the semiconductor device portion and a second electrode plate. The method includes a sealing step of forming a sealed composite body by covering target surfaces of a composite body formed by the first bonding step with resin, the target surfaces being surfaces other than a second surface of the first electrode plate and the second surface of the semiconductor device portion. The second bonding step is performed after the sealing step.

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.

Abstract: There is provided semiconductor package including: an internal lead having at least one electronic component mounted on a surface thereof; a heat sink disposed below the internal lead; a molded portion sealing the at least one electronic component, the internal lead and the heat sink; an external lead extended from the internal lead and protruding outwardly from the molded portion in a radial direction; a heat radiating member attached to the heat sink and a surface of the molded portion; and an insulating coating film formed on a surface of the external lead.

Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.

Abstract: In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.

Abstract: A semiconductor system (100) comprises a first component including a first semiconductor chip (110) attached to the pad (120) of a leadframe made of a first metal sheet of high thermal conductivity, and a second component including a second semiconductor chip (140) attached to the pad (150) of a leadframe made of a second metal sheet wire-bondable on both surfaces. Wires (160) connect chip (140) to leads (151) at the surface (151a) facing the chip. A polymeric housing (170) encapsulates chip (140) and wires (160), leaving un-encapsulated the lead surface (151b) facing away from chip (140). Housing (170) is attached to the first chip (110) using a layer (180) of low thermal conductivity, and lead surfaces (151 b), facing away from the first chip (110), are connected by wires (131) to leads (121) of the first metal leadframe.

Abstract: An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die.

Abstract: A semiconductor device has high reliability which suppresses a temperature rise of a set housing within an allowable range, and avoids an effect on a wiring on a package substrate due to thermal expansion of a heat dissipating member. The semiconductor device includes a semiconductor element, a package substrate, and a heat dissipating member. A first main surface of the semiconductor element faces an element-mounting surface of the package substrate and is connected to the package substrate. A main surface part of the heat dissipating member contacts a second main surface which is a back surface of first main surface of semiconductor element. A bonding part around a periphery of the main surface part is bonded to a bonding area of the element-mounting surface of the package substrate. A wiring on the package substrate is arranged at a portion other than the element-mounting surface, in a region of the bonding area.

Abstract: A combined diode, lead assembly incorporating two expansion joints. The combined diode, lead assembly incorporating two expansion joints includes a diode having a first diode terminal and a second diode terminal, a first conductor and a second conductor. The first conductor includes a first terminal that is electrically coupled to the diode at the first diode terminal and a second terminal that is configured as a first expansion joint, which is configured to electrically couple to a first interconnecting-conductor and is configured to reduce a stress applied to the diode by the first conductor. The second conductor includes a first terminal that is electrically coupled to the diode at the second diode terminal and a second terminal that is configured as a second expansion joint, which is configured to electrically couple to a second interconnecting-conductor and is configured to reduce a stress applied to the diode by the second conductor.

Abstract: A semiconductor device includes a first semiconductor chip, a buffer body, and a terminal lead. The first semiconductor chip includes a first electrode and a second electrode provided on a side opposite to the first electrode. The first semiconductor chip is configured to allow a current to flow between the first electrode and the second electrode. The buffer body includes a lower metal foil, a ceramic piece, and an upper metal foil. The lower metal foil is electrically connected to the second electrode. The ceramic piece is provided on the second electrode with the lower metal foil interposed. The upper metal foil is provided on a side of the ceramic piece opposite to the lower metal foil to be electrically connected to the lower metal foil. The terminal lead has one end provided on the upper metal foil and electrically connected to the upper metal foil.

Abstract: Film-on-wire (FOW) based IC devices and FOW based methods for IC packaging are described. In an embodiment, a method for packaging an IC dies involves applying a film layer to IC dies and bond wires that are attached to a substrate or a leadframe to form a film-on-wire layer, where the IC dies and the bond wires are enclosed by the film-on-wire layer, and cutting the substrate or the leadframe into IC devices. Other embodiments are also described. The FOW based method for IC packaging can eliminate the need for molding in the IC packaging process and consequently, can reduce the cost of IC packaging and the dimensions of packaged IC devices.

Abstract: A heat spreader frame is provided including: heat spreaders having upper surfaces; a peripheral frame surrounding the heat spreaders; spreaders, the peripheral frame having stand-off legs; tie bars having upper surfaces and a pin identifier at an end portion of the tie bars, the heat spreaders connected to one another and to the peripheral frame by the tie bars, the width of the stand-off legs wider than widths of the tie bars; at least portions of the upper surfaces of the tie bars being thinned to reduce heights of the tie bars; the upper surfaces of the heat spreader in an elevated position supported by the peripheral frame; and the heat spreaders and the tie bars covered by an package molding compound exposing the upper surface of the heat spreaders and one surface of the pin identifier coplanar to the upper surfaces of the heat spreaders.

Abstract: Embodiments of the present disclosure describe semiconductor device packaging techniques and devices that incorporate a heat spreader into the insulating material of a packaged semiconductor device. In one embodiment, a device comprising a semiconductor device is coupled to a substrate, and insulating material covers (i) a portion of the semiconductor device and (ii) a portion of the substrate. The device also comprises a heat spreader embedded in the insulating material and the heat spreader is isolated from the substrate at least in part by the insulating material.