Abstract: A semiconductor module with two cooling surfaces and method. One embodiment includes a first carrier with a first cooling surface and a second carrier with a second cooling surface. The first cooling surface is arranged in a first plane, the second cooling surface is arranged in a second plane, at an angle different from 0° relative to the first plane.

Abstract: A load driving semiconductor apparatus includes: a driving transistor, which operates based on an input voltage from an external circuit; a power semiconductor device controlling power supply to a load in such a manner that the power semiconductor device supplies electric power to the load when the transistor operates, and the power semiconductor device stops supplying electric power to the load when the transistor stops operating; and a mounting board, on which the driving transistor and the power semiconductor device are mounted. The mounting board includes a heat radiation pattern for emitting heat generated in the power semiconductor device. The heat radiation pattern includes a heat receiving pattern, on which the driving transistor is mounted.

Abstract: A chip package and a process thereof are provided. The chip package includes a lead frame, a heat sink, a chip and a molding compound. The lead frame includes a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface opposite thereto. The heat sink has a third surface and a fourth surface opposite thereto, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed. The chip is disposed on the first surface of the chip pad and electrically connected to each of the chip pad and the leads. The molding compound encapsulates the chip, the chip pad, the heat sink and a portion of each of the leads.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.

Abstract: One aspect relates to a power semiconductor arrangement includes a power semiconductor module which is mechanically connected to a heat sink. In order to improve the thermal cycling stability of the connection between a baseplate of the module and a circuit carrier connected thereto, recesses are provided in the baseplate. One aspect further relates to a power semiconductor module.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A molded integrated circuit package is described. The molded integrated circuit package comprises a substrate having a plurality of contacts on a first surface; a die having a plurality of solder bumps on a first surface, the plurality of solder bumps being coupled to the plurality of contacts on the first surface of the substrate; an adhesive material positioned on a second surface of the die; a lid attached to the adhesive material; and an encapsulant positioned between the lid and the substrate. Methods of forming molded integrated circuit packages are also disclosed.

Abstract: Assemblies for dissipating heat from integrated circuits and circuit chips are disclosed. The assemblies include a low melt solder as a thermal interface material (TIM) for the transfer of heat from a chip to a heat sink (HS), wherein the low melt solder has a melting point below the maximum operating temperature of the chip. Methods for making the assemblies are also disclosed.

Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.

Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. The semiconductor package may include: an insulator that has first and second opening parts; an active element that is disposed inside the first opening part; a passive element that is disposed inside the second opening part; a protective member that is disposed at a lower part of the insulator and covers a lower part of the passive element; a build-up layer that is disposed on the insulator and electrically connected to the active element; and an external connection unit that is electrically connected to the build-up layer.

Abstract: Methods and apparatus for integrated circuit (IC) packages with improved thermal performance and input/output capabilities are described. An integrated circuit (IC) package includes a leadframe, an IC die, a substrate having opposing first and second surfaces, a first wirebond, and a second wirebond. The leadframe includes a die attach pad having opposing first and second surfaces and a plurality of leads that emanate in an outward direction from the die attach pad. The IC die is coupled to the first surface of the die attach pad. The substrate is coupled to the die attach pad. Contact pads on the first surface of the substrate are electrically connected to bond fingers on the second surface of the substrate. The first wirebond couples a first bond pad on a first surface of the IC die to a bond finger on the second surface of the substrate. The second wirebond couples a second bond pad on the first surface of the IC die to a lead of the plurality of leads.

Abstract: A resin sealing semiconductor device (2) having a structure in which a portion to be sealed of components including a plurality of chip mounting board, a semiconductor chip mounted to a front surface of each chip mounting board, and a plurality of leads provided correspondingly to each chip mounting board is embedded in resin molded portions (41 and 42) molded into a generally plate shape, and outer lead portions of the plurality of leads (16 and 17) are led out in line from a side surface at one end in a width direction of the resin molded portions, and back surfaces as exposed surfaces (11u1 to 11w1 and 12u1 to 12w1) of each chip mounting board are placed on one surfaces of the resin molded portions (41 and 42), wherein a plurality of positioning protrusions (50) are provided on one surfaces of the resin molded portions (41 and 42), and a protrusion height of the positioning protrusions is set so that a gap to be filled with insulating resin is formed between each part of the exposed surface of each chip mo

Abstract: A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements 1. In the resin-sealing step, in a state where the thermal conductor is arranged with its concavity facing up and the concavity of the thermal conductor is filled with a liquid resin, the semiconductor elements are clipped in the liquid resin in the concavity and the liquid resin is solidified.

Abstract: A heat-dissipating structure and a heat-dissipating semiconductor package having the same are disclosed in the present invention. The heat-dissipating semiconductor package includes a chip carrier, a flip chip semiconductor chip attached and electrically connected to the chip carrier, and a heat sink bonded to the flip chip semiconductor chip via a thermal interface material, such as a solder material, wherein a groove is formed on the heat sink around the bonding area of the thermal interface material, and a blocking layer, such as a metal oxide layer, is formed on the surface of the groove to reduce the wetting capability of the thermal interface material, thus further prevents the thermal interface material from wetting the groove in the fusion process performed the thermal interface material, therefore, it ensures the thermal interface material has sufficient thickness for forming solder bonding between the heat sink and the flip chip semiconductor chip.

Abstract: In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.

Abstract: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.

Abstract: Provided is a device capable of oscillating a plurality of oscillation modes within a laser medium for obtaining a fundamental wave output which is easy in output scaling and high in luminance, thereby enabling a second harmonic conversion which is high in efficiency. The device includes: a laser medium (5) that is planar, has a waveguide structure in a thickness direction of a cross-section that is perpendicular to an optical axis (6), and has a cyclic lens effect in a direction perpendicular to the optical axis (6) and the thickness direction; a clad (4) that is bonded onto one surface of the laser medium (5); and heat sink (3) that is bonded onto one surface side of the laser medium (5) through the clad (4), and in the device, a laser oscillation includes a laser oscillation that oscillates in a waveguide mode of the laser medium (5), and a laser oscillation that oscillates in a plurality of resonator modes that are generated by a cyclic lens effect of the laser medium (5).

Abstract: An apparatus for heatsink attachment and a method for forming the apparatus. The apparatus includes a substrate, a semiconductor chip on top of and physically attached to the substrate, and a lid on top of the substrate. The lid includes a first thermally conductive material. The apparatus further includes a heatsink on top of the lid. The heatsink includes a second thermally conductive material. The semiconductor chip and the substrate share a common interface surface that defines a reference direction perpendicular to the common interface surface and pointing from the substrate towards the semiconductor chip. The lid is disposed between the substrate and the heatsink. The lid includes a first protruding member. The first protruding member of the lid is farther away from the substrate than a portion of the heatsink in the reference direction.

Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract: A method includes: mounting a plurality of semiconductor elements on a substrate having wirings; connecting electrically electrodes of the semiconductor elements and the wirings; sealing the semiconductor elements with a resin, which is carried out by bringing a thermal conductor having a concavity and the substrate to be in contact with each other so that the semiconductor elements are positioned within the concavity and by filling the concavity with the resin; and separating respective semiconductor elements 1. In the resin-sealing step, in a state where the thermal conductor is arranged with its concavity facing up and the concavity of the thermal conductor is filled with a liquid resin, the semiconductor elements are dipped in the liquid resin in the concavity and the liquid resin is solidified.

Abstract: A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe.

Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.

Abstract: A lead frame unit, a semiconductor package having a lead frame unit, a stacked semiconductor package having a semiconductor package, and methods of manufacturing the same are provided. The lead frame unit in a stacked semiconductor package may include a die pad supporting a semiconductor chip, an inner lead electrically connected to the semiconductor chip, an outer lead extending from the inner lead, and a heat-resistant insulation member surrounding the connection portion. The outer lead may include a connection portion connected to the inner lead and a junction portion connected to the connection portion and a circuit board. An external signal may be applied to the junction portion. If the lead frame unit is used in the stacked semiconductor package, the outer lead and a dummy outer lead in the stacked semiconductor package may have substantially the same shape.

Abstract: A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of a semiconductor die. The semiconductor device also includes a second heat sink that is configured as a conductive clip. The conductive clip is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks.

Abstract: The invention can be used for improving performance of laser diodes, solar cells, microprocessors and other devices. The invention enables to create semiconductor devices having a great area of die, a great number of leads, a high operating current and a high heat dissipation. This is achieved by the following manner: offered leads are made of copper foil; the rigidity of the foil is decreased by means of disposing of alternating parallel narrow trenches on both sides of the foil; the offered leads are microspring; additional decreasing of rigidity can be achieved by the bending of foil along wide trenches that are created for this aim. Offered leads can be directly connected to the die.

Abstract: In an embodiment, an integrated heat sink for a microchip includes a substrate having a plurality of interconnected electronic devices formed in a plurality of layers. At least one heat sink element is interposed within the layers and includes a microchannel to provide a fluid flow path for heat transfer. Other embodiments include a method of making an integrated heat sink for a microchip.

Abstract: Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented.

Abstract: A semiconductor device is provided which comprises a thermally radiative and electrically conductive support plate 1; and a regulatory semiconducting element 2 mounted on one main surface of support plate 1 through an insulator 3. Insulator 3 comprises an insulative layer 3a mounted on support plate 1 and an adiabatic layer 3b interposed between insulative layer 3a and regulatory semiconducting element 2 to fully protect regulatory semiconducting element 2 from heated environment therearound in the semiconductor device.

Abstract: A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.

Abstract: An arrangement for cooling a power semiconductor module, the power semiconductor module having a substrate with a ceramic plate and may have a metallization thereon, the arrangement has a container for the intake of a coolant with a heat-conducting plate; the heat-conducting plate having two sides, one side joined to the metallization of the substrate and the other side being in contact with the coolant; wherein the heat-conducting plate is made of materials having a metal matrix composite (MMC) material with a filling content, which results in a thermal expansion of below that of copper.

Abstract: In an exemplary embodiment, a packaged device having enhanced thermal dissipation characteristics includes a semiconductor chip having a major current carrying or heat generating electrode. The semiconductor chip is oriented so that the major current carrying electrode faces the top of the package or away from the next level of assembly. The packaged device further includes a conductive clip for coupling the major current carrying electrode to a next level of assembly, and a heat spreader device formed on or integral with the conductive clip. A portion of the heat spreader device may be optionally exposed.

Abstract: A multichip module buck converter 10 has a high side power mosfet 12, a low side power mosfet 22 and a pre-molded leadframe 40 between the two mosfets for connecting the source of mosfet 12 to the drain of mosfet 22. Clips 14, 16, 18 and 26 carry the source, gate and drain terminals of the mosfet from planes parallel but spaced apart to a common plane.

Abstract: A heat dissipation plate having a lamination of a copper layer, a molybdenum layer and a graphite layer, and outer copper layers each provided on a surface of the lamination, is disclosed. And also a semiconductor device using the heat dissipation plate is disclosed.

Abstract: Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

Abstract: A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost.

Abstract: In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Abstract: There is provided a method of forming a component package. The method includes the steps of providing the die pad or heat sink, forming an isolation layer on the rear surface of the die pad or heat sink and encapsulating the die pad with encapsulating material in a mold cavity after forming the isolation layer on the rear of the die pad or heat sink.

Abstract: A power semiconductor module and a method of manufacture thereof includes a lead frame carrying lead having inner and outer lead portions. The outer lead portions, which are connected by soldering to semiconductor chips simultaneously, eliminate the need for using bonding wires. Since no bonding wire is used for connecting the leads and the semiconductor chips, a sufficient current capacity is obtained. The bonding between an insulating circuit board and the semiconductor chips and the bonding between the semiconductor chips and the leads can be made simultaneously in a single step of reflow-soldering. As a result, the mounting time can be shortened and the power semiconductor module can be manufactured more efficiently.

Abstract: Methods, apparatus and assemblies for enhancing heat transfer in electronic components using a flexible thermal pillow. The flexible thermal pillow has a thermally conductive material sealed between top and bottom conductive layers, with the bottom layer having a flexible reservoir residing on opposing sides of a central portion of the pillow that has a gap. The pillow may have roughened internal surfaces to increase an internal surface area within the pillow for enhanced heat dissipation. In an electronic assembly, the central portion of the pillow resides between a heat sink and heat-generating component for the thermal coupling there-between. During thermal cycling, the flexible reservoir of the pillow expands to retain thermally conductive material extruded from the gap, and then contracts to force such extruded material back into the gap. An external pressure source may contact the pillow for further forcing the extruded thermally conductive material back into the gap.

Abstract: Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Abstract: A heat slug includes a heat spreading member and a supporting member. The supporting member extends outwardly from the edge of the heat spreading member. The tips of the supporting member are formed with a plurality of contact portions, wherein each said contact portion has a bottom face inclined to the surface of the chip carrier art an angle of more that 5 degrees.

Abstract: A package-on-package system includes: providing a base substrate; mounting an integrated circuit on the base substrate; positioning a stacking interposer over the integrated circuit; and forming a heat spreader base around the integrated circuit by coupling the base substrate and the stacking interposer to the heat spreader base.

Abstract: A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body.

Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.

Abstract: A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.

Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.