Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: A method of forming a semiconductor device includes forming a field-effect transistor (FET), and forming a fuse which includes a graphene layer and is electrically connected to the FET.

Abstract: On a silicon substrate 120 of a semiconductor device, a field oxide film 101 is provided. On the field oxide film 101, two fuses 104 are provided. Directly below the fuses 104 in the silicon substrate 120, an n-type well 102 is provided. Besides the n-type well 102, a p-type well 103 is provided in such a manner as to surround a region directly under the fuses 104 in the silicon substrate 120. A cover insulating film 108 is provided over the silicon substrate 120 and the field oxide film 101. A seal ring composed of a contact 106 and an interconnection 107 is embedded in the cover insulating film 108 so as to surround the fuses 104.

Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

Abstract: An anti-fuse device includes a gate electrode on a semiconductor substrate, a gate insulating layer between the semiconductor substrate and the gate electrode, junction regions in the semiconductor substrate adjacent the gate electrode, and at least one anti-breakdown material layer between the junction regions, the gate insulating layer being between the gate electrode and the anti-breakdown material layer.

Abstract: Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.

Abstract: An electronic circuit arrangement has a substrate which has at least one metallization layer. At least one electrical interconnect and/or at least one via are formed in the metallization layer such that the electrical interconnect and the via are in the form of an electrical fuse link. In addition, the substrate has electrical circuit components which are arranged in the circuit layer. The circuit components are electrically coupled to one another by means of the electrical interconnect and by means of a plurality of vias.

Abstract: A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.

Abstract: An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.

Abstract: Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.

Abstract: An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mx metal to the Mx+1 metal in a vertical orientation.

Abstract: Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

Abstract: A repairable memory cell in accordance with one or more embodiments of the present disclosure includes a storage element positioned between a first and a second electrode, and a repair element positioned between the storage element and at least one of the first electrode and the second electrode.

Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Abstract: The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad includes a coating on an upper surface. A dielectric layer is formed over the bond pad and the fuse layer. A passivation layer is formed over the dielectric layer. An etch is performed to form a bond pad opening and a fuse opening. The etch is performed using only a single mask. The fuse opening defines a fuse window. The upper surface of the bond pad is exposed by substantially removing the coating from the entire upper surface.

Abstract: A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Abstract: A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.

Abstract: A semiconductor device having an electrical fuse which is cut in a reliable manner and a method for manufacturing it. The electrical fuse is a multilayer structure which includes a polysilicon film and a metal silicide film such as a tungsten silicide film. By applying an electric current with a density of 40 mA/?m3 or more to the electrical fuse with a prescribed length, the fuse is cut by electromigration and a pinch effect in a reliable manner.

Abstract: A semiconductor device includes a field-effect transistor (FET), and a fuse which includes a graphene layer and is electrically connected to the FET.

Abstract: The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.

Abstract: A manufacturing method of a display device including a gate electrode film, a first electrode film, a second electrode film, and a conductive film connected to the first electrode film and formed of a conductive layer including a first conductive layer and a second conductive layer formed overlapping the first conductive layer. The method includes the steps of forming the first electrode film and the second electrode film, forming the conductive layer such that the conductive layer is connected to the first electrode film and the second electrode film, and forming the conductive film by removing regions other than predetermined regions of the conductive layer, wherein the conductive layer forming step includes the steps of forming the first conductive layer on the respective upper surfaces of the first electrode film and the second electrode film and forming the second conductive layer on the upper surface of the first conductive layer.

Abstract: Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.

Abstract: A semiconductor integrated circuit includes: a normal fuse cell array programmed with a normal fuse data; a dummy fuse cell array programmed with a verifying fuse data; and a sensor configured to read the verifying fuse data from the dummy fuse cell array and read the normal fuse data from the normal fuse cell array, wherein the normal fuse cell array is configured to be read according to a reading result of the dummy fuse cell array.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A semiconductor device include an insulating interlayer formed over a substrate; an electrical fuse which is composed of a first wiring formed in the insulating interlayer, and has a cutting portion; and a second wiring and a third wiring, formed respectively on both sides of the cutting portion to extend along the cutting portion in the same layer as the first wiring. Air gaps formed to extend along the cutting portion are respectively provided between the cutting portion and the second wiring and between the cutting portion and the third wiring.

Abstract: In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: The present invention provides a semiconductor device realizing reliable cutting of a fuse without enlarging layout area of a fuse element and the reduced number of wiring layers of a preventing wall that prevents diffusion of fuse copper atoms. A fuse is formed by using a wire in a metal wiring layer as an upper layer in a plurality of metal wiring layers. Wires are disposed just above and just below a fuse each with a gap of at least two wiring layers. In an upper layer, a power wire that transmits power supply voltage is used as a part covering a preventing wall structure just above the fuse.

Abstract: A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract: Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.

Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

Abstract: A MEMS device can include an actuator, a base formed from a substrate, and a plurality of memory cells integrated with the base. At least a portion of the base can be configured to move in response to the actuator. A miniature camera can include a base comprising a frame, a stage, and a plurality of flexures configured to connect the stage with the frame. The flexures can be adapted to bend to permit the stage to move relative to the frame. The camera can include a plurality of memory cells integrated with the base, a lens mount secured to the stage, a lens barrel secured to the lens mount, an image sensor, and an actuator adapted to move the stage relative to the frame and the image sensor.

Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.

Abstract: A MEMS device includes a substrate, an insulating layer section formed above the substrate and having a cavity, a functional element contained in the cavity, and a fuse element contained in the cavity and electrically connected with the functional element. It is preferable that the fuse element is spaced apart from the substrate.

Abstract: An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.

Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.

Abstract: The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered. A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.