Abstract: An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Abstract: A power semiconductor arrangement has an electrically insulating and thermally conductive substrate, which is provided with structured metallization on at least one side, a cooling device which is in thermal contact with the other side of the substrate, at least one semiconductor component which is arranged on the substrate and is electrically connected to the structured metallization, an entirely or partially electrically insulating film which is arranged at least on that side of the substrate at which the at least one semiconductor component is placed, and which is laminated without any cavities onto the substrate including or excluding the at least one semiconductor component, and a contact-pressure device which exerts a force on the substrate locally and via the at least one semiconductor component such that the substrate is pressed against the cooling device.

Abstract: A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.

Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

Abstract: A semiconductor module has a coupling substrate which is used for the internal electrical coupling of an integrated circuit on adjacent semiconductor chips. The semiconductor chips have integrated circuits and are arranged on a mount structure. The semiconductor chips are externally connected to external contacts. The coupling substrate overlaps edge areas of the adjacent semiconductor chips.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A semiconductor device including a first semiconductor element mounted on a first surface of second semiconductor element, wherein solder balls are formed on the first surface of the second semiconductor element such that the first surface includes an area without solder balls. At least one first semiconductor element is mounted to the second semiconductor element at the area of the first surface without solder balls. The at least one first semiconductor element may be mounted to the second semiconductor element using solder joints.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A semiconductor device is provided which comprises a connecting lead 4 mounted between a MOS-FET 1 and a regulatory IC 2 on a support plate 3. Connecting lead 4 has a thermally radiative and electrically conductive substrate 6 and electrically insulative and thermal transfer-resistive covering 7. Substrate 6 has one end 6a providing one main surface 4a of connecting lead 4 which is mounted and electrically connected on the other main surface 1b of MOS-FET 1. Covering 7 provides the other main surface 4b of connecting lead 4 for supporting regulatory IC 2 at one end 6a of substrate 6.

Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: In display devices using thin film transistors, a graphoepitaxy is used for a semiconductor layer crystallizing process. Thus, a display device in which crystallinity is improved, a variation in characteristics of thin film transistors is reduced, display nonuniformity is less, and a display quality is superior is provided. Steps are formed on a substrate in advance and an amorphous silicon film is formed thereon, and then laser crystallization is conducted in a direction perpendicular to the steps.

Abstract: A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas.

Abstract: A circuit arrangement for a power semiconductor module provides low parasitic inductances and low loss. An electrically insulating substrate supports metallic ribbon connectors which in turn power attached semiconductor components. DC port conducts are positioned in close proximity to each other and are arranged in at least one partial sector parallel and in close proximity to the surface of the substrate and/or the ribbon connectors and electrically insulated from the same, and at least one AC port conductor is similarly attached. The port conductors include surface elements enabling simplified low-inductance wire bond connection from the port conductors to either the power semiconductor components or ribbon connectors or both.