Abstract: An LED unit comprises a substrate and a first LED chip. The first LED chip may include a first light-emitting surface arranged on the substrate in such a way that light emitted from the first LED chip radiates in a direction of radiation of the LED unit. The LED unit includes a second LED chip comprising a second light-emitting surface and arranged above the first LED chip in such a way that the second LED chip at least partially covers the first LED chip and radiates light emitted from the second LED chip in the direction of radiation of the LED unit. The LED unit comprises a first conversion layer at least partially covering the first light-emitting surface and/or at least partially laterally surrounding the first LED chip. A second conversion layer at least partially covers the second LED chip.

Abstract: A flexible LED lighting device is disclosed that includes a flexible LED light bar surrounded by a flexible conduit. The flexible LED light bar fits within a inner channel of the flexible conduit in an elongated direction and includes sets of LED arrays on opposed sides of a flexible elongate circuit board formed from a continuous wire band and circuit board segments. Preferably, the flexible conduit includes a tubular outer sleeve that surrounds a tubular inner sleeve and the tubular inner sleeve and LED light bar are cable of being displaced in a radial directions relative to the outer sleeve or in directions that are substantially orthogonal to the elongated direction. The flexible conduit is translucent and/or patterned to diffuse or scatter light emitted from the LED light bar to provide full-body illumination.

Abstract: A gastrectomy device includes an elongated member and a tube. The elongated member has a proximal end and a distal end and defines a longitudinal side window disposed adjacent the distal end. The elongated member defines a first longitudinal channel, a second longitudinal channel, and a plurality of side apertures. The first longitudinal channel is in communication with the longitudinal side window and the plurality of side apertures is in communication with the second longitudinal channel. The tube extends through the first longitudinal channel. An array of lights is associated with the tube to provide illumination. The tube is movable through the elongated member between a first state, in which the tube is disposed within the first longitudinal channel of the elongated member, and a second state, in which a portion of the tube extends through the longitudinal side window of the elongated member.

Abstract: Provided is a concentrating lens of a light emitting diode lamp comprising a lens body. The lens body comprises a top portion, a bottom portion opposite the top portion, a light output surface positioned on the top portion, an optical surface formed concavely on the light output surface, and a light input surface concavely formed on the bottom portion and towards the top portion. The light input surface is disposed on a same axis with the optical surface. The light input surface comprises a light input side plane and a light input concave plane connected with the light input side plane. The concentrating lens is capable of distributing the light of LED to positions on each of the side walls of a light box close to and distal from the LED, and allowing the light emitted from the LED to lighten the light box uniformly.

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract: A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract: A method of forming a semiconductor device package includes removing a portion of a first connector and a molding compound surrounding the first connector to form an opening, wherein the first connector is part of a first package, and removing the portion of the first connector comprises forming a surface on the first connector which is at an angle with respect to a top surface of the molding compound. The method further includes placing a second connector in the opening, wherein the second connector is part of a second package having a semiconductor die. The method further includes bonding the second connector to a remaining portion of the first connector.

Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.

Abstract: An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: A semiconductor package comprises a board including a board pad, a plurality of semiconductor chips mounted on the board, the semiconductor chips including chip pads. Bumps are disposed on the chip pads, respectively, and a wire is disposed between the chip pads and the bumps. The wire electrically connects the chip pads of the plurality of semiconductor chips and the board pad to each other.

Abstract: A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.

Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.

Abstract: A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package.

Abstract: Provided is a multilayered semiconductor device, including: a first semiconductor package including a first semiconductor element and a first wiring board; a second semiconductor package including: a second semiconductor element, a second wiring board and a first encapsulating resin for encapsulating the second semiconductor element therein; and a plate member disposed between the first semiconductor package and the second semiconductor package, the first semiconductor package, the plate member, and the second semiconductor package being stacked in this order, in which the first wiring board and the second wiring board are electrically connected to each other via a metal wire through one of a notch and an opening formed in the plate member and the first semiconductor element, the second semiconductor package, and the metal wire are encapsulated in a second encapsulating resin.

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract: A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact.

Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of writings. A semiconductor device includes a second transistor and a capacitor provided over a first transistor. A source electrode of the second transistor which is in contact with a gate electrode of the first transistor is formed using a material having etching selectivity with respect to the gate electrode. By forming the source electrode of the second transistor using a material having etching selectivity with respect to the gate electrode of the first transistor, a margin in layout can be reduced, so that the degree of integration of the semiconductor device can be increased.

Abstract: A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

Abstract: There are disclosed herein various implementations of semiconductor packages having a selectively conductive film interposer. In one such implementation, a semiconductor package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, a selectively conductive film interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The selectively conductive film interposer may be configured to serve as an interposer and to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors.

Abstract: One aspect provides an integrated circuit (IC) packaging assembly that comprises a substrate having conductive traces located thereon, wherein the signal traces are located in an IC device region and the power traces are located in a wafer level fan out (WLFO) region located lateral the IC device region. This embodiment further comprises a first IC device located on a first side of the substrate within the IC device region and that contacts the signal traces in the IC device region. A second IC device is located on a second side of the substrate opposite the first side and overlaps the IC device region and the WLFO region. The second IC device contacts a first portion of the signal traces in the IC device region and contacts a first portion of the power traces in the WLFO region.

Abstract: Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate including at least one contact pad; an external chip laminate which includes a plurality of semiconductor chips mounted on the substrate, and which is stacked in multi-steps such that the ends at one side of the plurality of semiconductor chips alternately protrude in opposite directions to expose bonding pads which are formed on the up-face surface; at least one internal chip which is disposed in a mounting space formed between the external chip laminate and substrate so as to be electrically connected to the substrate; and a conductive wire electrically connecting the bonding pad of the semiconductor chip and the contact pad of the substrate.

Abstract: Provided is a stacked semiconductor package.

Abstract: A semiconductor device includes a first wiring board, a first semiconductor element mounted on the first wiring board, a second wiring board disposed over the first semiconductor element, and a second semiconductor element mounted on the second wiring board. The wiring boards are electrically interconnected by a connecting portion interposed therebetween. A resin layer is formed between the wiring boards such that the first semiconductor element mounted on the first wiring board is sealed and such that the wiring boards having the respective semiconductor elements mounted thereon are bonded together.

Abstract: The described embodiments of forming bonding structures for package on package involves removing a portion of connectors and molding compound of the lower package. The described bonding mechanisms enable easier placement and alignment of connectors of an upper package to with connector of a lower package. As a result, the process window of the bonding process is wider. In addition, the bonding structures have smoother join profile and planar joint plane. As a result, the bonding structures are less likely to crack and also are less likely to crack. Both the yield and the form factor of the package on package structure are improved.

Abstract: A semiconductor device includes a first semiconductor device and second semiconductor device stacked on the first semiconductor device. The first semiconductor device includes a first interconnect substrate, a first semiconductor element provided on an upper surface of the first interconnect substrate, a first electrode provided on the upper surface of the first interconnect substrate, and an insulating layer having an opening portion through which part of the first electrode is exposed. The second semiconductor device includes a second interconnect substrate, a second semiconductor element provided on an upper surface of the second interconnect substrate, a second electrode provided on a lower surface of the second interconnect substrate, and an inter-device connection terminal connected to the second electrode. Part of the first electrode exposed through the opening portion has a smaller area than an area of the opening portion.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.

Abstract: An optoelectronic component (100) comprises a first semiconductor layer stack (101), which has an active layer (110) designed for the emission of radiation and a main area (111). A separating layer (103) is arranged on said main area, said separating layer forming a semitransparent mirror. The optoelectronic component comprises a second semiconductor layer stack (102), which is arranged at the separating layer and which has a further active layer (120) designed for the emission of radiation.

Abstract: A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.

Abstract: Systems and methods of the present disclosure provide for three-dimensional stacks of microelectromechanical (MEMS) systems, such as sensors. The stacks may be encapsulated and sealed, and can be positioned within biological tissue, for example to monitor biological signals within the volume of the sensor, provide stimulating signals to a brain, and so forth.

Abstract: A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.

Abstract: A layered chip package includes a main body. The main body includes a main part, and further includes first terminals and second terminals disposed on the top and bottom surfaces of the main part, respectively. The main part includes first and second layer portions, and through electrodes penetrating them. The through electrodes are electrically connected to the first and second terminals. Each of the layer portions includes a semiconductor chip having a first surface and a second surface opposite thereto, and further includes surface electrodes. The surface electrodes are disposed on a side of the semiconductor chip opposite to the second surface. The first and second layer portions are bonded to each other such that the respective second surfaces face each other. The first terminals are formed by using the surface electrodes of the first layer portion. The second terminals are formed by using the surface electrodes of the second layer portion.

Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.

Abstract: This disclosure related to a stacked chip package structure having a sloped dam structure located on the substrate and beside the chip stack. The dam structure can facilitate the dispensing process of the underfill.

Abstract: The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate. Spacers are provided between the first and second substrates. A seal material is formed outside the matrix circuits and the peripheral driver circuits in the first and second substrates. A protective film is formed on the peripheral driver circuit has substantially a thickness equivalent to an interval between the substrates which is formed by the spacers.

Abstract: A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

Abstract: An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.

Abstract: A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

Abstract: The invention pertains to a method for manufacturing a microelectronic device on a substrate comprising at least one first electrical component and one second electrical component distributed respectively in first and second levels stacked one on top of the other on the substrate, this method comprising: the manufacture of at least one first arm and one second arm of different lengths, each of these arms directly and mechanically linking an electrical pad to a fixed anchoring point on the substrate, and the electrical pad is made inside the first level and then shifted, prior to the electrical connection of the second component, to a position of connection wherein the upper face of the electrical pad is in contact with the interior of the second level parallel to the substrate.

Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.