Abstract: A microelectronic assembly and related method of forming a through hole extending through a first wafer and a second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers. A hole can be etched downwardly through the first wafer until a gap is partially exposed between the confronting faces of the first and second wafers. The hole can have a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening through which the interfacial gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered such that at least some of the sputtered material deposits onto at least one of the exposed confronting faces of the first and second wafers and provides a wall between the confronting faces.

Abstract: A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Abstract: A module is disclosed. In one embodiment, the module is a memory module including a first multichip package, the first multichip package including a first master chip and a first plurality of slave chips, and a second multichip package, the second multichip package including a second master chip and a second plurality of slave chips. A first through via passes through the first master chip and electrically connects to the first master chip to provide a supply voltage to the first master chip. A second through via passes through the first master chip without being electrically connected to provide a supply voltage to the first master chip. A first set of additional through vias pass through respective ones of the first plurality of slave chips and electrically connect to the respective ones of the first plurality of slave chips, wherein the second through via and first set of additional through vias are aligned to form a first stack of through vias.

Abstract: A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips.

Abstract: A RF system which includes a silicon substrate formed with at least one via-hole filled with conductive material so that both sides of the silicon substrate are electrically connected with one another; at least one flat device formed on one side of the silicon substrate; and at least one RF MEMS device formed on the other side of the silicon substrate.

Abstract: A chip stack may include a first chip and a second chip stacked on the first chip. Each of the first and second chips may include a substrate having an active surface and an inactive surface opposite to the active surface; an internal circuit in the active surface; an I/O chip pad on the active surface and connected to the internal circuit through an I/O buffer; and a I/O connection pad connected to the I/O chip pad through the I/O buffer by a circuit wiring. A redistributed I/O chip pad layer may be on the active surface of the first chip, the redistributed I/O chip pad layer redistributing the I/O chip pad. The I/O connection pads of the first chip and the second chip may be electrically connected to each other by an electrical connecting part.

Abstract: A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable.

Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.

Abstract: Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies.

Abstract: In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the first electrode pads are exposed. Support members support a back surface of a protruding portion of the second semiconductor chip through the insulating member.

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.

Abstract: Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.

Abstract: In one embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes forming a cured film of an insulation resin on a surface of a first semiconductor chip and flip-chip bonding a second semiconductor via a bump on the first semiconductor chip on which the cured film of the insulation resin is formed. The insulation resin can be cured at temperature range from (A?50)° C. to (A+50)° C., wherein “A” is a solidification point of the bump.

Abstract: An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.

Abstract: A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided.

Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established.

Abstract: A semiconductor device includes a semiconductor chip, a supporting body that is disposed below the semiconductor chip and supports the semiconductor chip, a spacer that is fixed onto the first semiconductor chip, and a substrate that is located below the first semiconductor chip and electrically connected to the semiconductor chip with a wire. At least a part of the peripheral portion of the semiconductor chip is an overhang portion that projects more laterally than the peripheral portion of the supporting body. A covering portion that covers a part of the upper surface of the overhang portion is formed in the spacer. The wire is connected to a region in the upper surface of the overhang portion, the region being lateral to the outermost periphery of the covering portion of the spacer and not being covered with the covering portion of the spacer.

Abstract: A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

Abstract: In one embodiment, a semiconductor package disclosed herein can be generally characterized as including a resin substrate having a first recess, a first interconnection disposed on a surface of the first recess, a first semiconductor chip disposed in the first recess, and an underfill resin layer substantially filling the first recess and covering a side surface of the first semiconductor chip. The first semiconductor chip is electrically connected to the first interconnection.

Abstract: In a first embodiment, an apparatus and a method of fabrication thereof includes a substrate, a controller formed on a first integrated circuit (IC) die and disposed on the substrate, a second IC die embodying circuitry configured to enable communication between the controller and an external device, first I/O pads disposed on the first IC die, second I/O pads disposed on the second IC die, wire bonding interconnections coupling at least one of the first I/O pads with at least one of the second I/O pads, and a memory array formed on a third IC die and configured to enable communication with the controller. In a second embodiment the memory array is alternatively integrated into the first IC die.

Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate and a second semiconductor chip mounted on top of the first semiconductor chip. The first chip includes a plurality of metal lines which may be deposited at its top surface, and the metal lines are isolated from circuitry in the first chip. Wire bonds connect pads on the second chip to metal lines on the first chip. Additional wired bonds connect the metal lines on the first chip to terminals on the substrate. Conductive through-silicon vias or solder bumps may replace the wire bonds, and additional chips may be included in the package.

Abstract: An electronic assembly adapted for forming package on package (PoP) devices includes a package substrate having a molded IC die thereon that defines a mold cap height and substrate contact pads lateral to the molded IC die. An interposer including an interposer substrate has bottom metal land pads and top metal land pads, interposer vias, and an open receptacle region formed through the interposer substrate. The substrate top surface is positioned relative to the interposer so that the molded IC die is within the open receptacle region to align the bottom metal land pads and substrate contact pads. An underfill layer is between the substrate top surface and the bottom side of the interposer substrate. A step height from the mold cap height minus a height of the top metal land pads is generally from 0 to 0.2 mm.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.

Abstract: A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.

Abstract: A substrate for a semiconductor package is provided having first and second core layers defining a cavity having an adhesive member and sized and shaped to receive a semiconductor chip. The semiconductor package further having a connection member formed on a bond finger and connected to a via pattern formed through the first and second core layers. A stack package is also provided having multiple substrates.

Abstract: A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.

Abstract: Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed.

Abstract: A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

Abstract: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.

Abstract: Methods, systems, and apparatuses for wafer-level package-on-package structures are provided herein. A wafer-level integrated circuit package that includes at least one die is formed. The wafer-level integrated circuit package includes redistribution interconnects that redistribute terminals of the die over an area that is larger than an active-surface of the die. Electrically conductive paths are formed from the redistribution interconnects at a first surface of the wafer-level integrated circuit package to electrically conductive features at a second surface of the wafer-level integrated circuit package. A second integrated circuit package may be mounted to the second surface of the wafer-level integrated circuit package to form a package-on-package structure. Electrical mounting members of the second package may be coupled to the electrically conductive features at the second surface of the wafer-level integrated circuit package to provide electrical connectivity between the packages.

Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate.

Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.

Abstract: Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.

Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Abstract: A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip, a second semiconductor package stacked on the first semiconductor package, the second semiconductor package having at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip, and at least one signal connection member disposed in the first sealing member of the first semiconductor package, the at least one signal connection member electrically connecting the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.

Abstract: A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity over the first substrate with the first substrate partially exposed within the cavity; and mounting an interposer including a central aperture over the package encapsulation and the first substrate with the central aperture over the cavity.

Abstract: Disclosed are premolded substrates for semiconductor die packages and methods of making such substrates. An exemplary premolded substrate comprises a leadframe having a first surface, a second surface, a central portion disposed between the first and second surfaces, and a plurality of electrically conductive leads disposed about the central portion; a body of electrically insulating material disposed in a portion of the central portion of the leadframe and between the leads of the leadframe; and an aperture disposed in the leadframe's central portion and between the leadframe's first and second surfaces.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package.