Abstract: A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A semiconductor device is composed of a pair of semiconductor chips (402, 404) arranged parallel on the same flat plane; a high voltage bus bar (21) bonded on the surface on the collector side of one semiconductor chip (402); a low voltage bus bar (23) connected to the surface on the emitter side of the other semiconductor chip (404) with a bonding wire (27); a first metal wiring board (24-1) connected to the surface on the emitter side of the semiconductor chip (402) with a bonding wire (26); a second metal wiring board (24-2) bonded on the surface on the collector side of the semiconductor chip (404); a third metal wiring board (24-3) connected to the first metal wiring board (24-1); a fourth metal wiring board (24-4) connected by being bent from an end portion of the second metal wiring board (24-2); and an output bus bar (24) having output terminals (405) extending from each end portion of the third metal wiring board (24-3) and that of the fourth metal wiring board (24-4).

Abstract: The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.

Abstract: A semiconductor device structure including a substrate, a resistor, and a first gate structure is provided. The substrate includes a resistor region and a metal-oxide-semiconductor (MOS) transistor region. The resistor is disposed on the substrate within the resistor region. The resistor includes a first dielectric layer, a metal layer, a second dielectric layer, and a semiconductor layer sequentially stacked on the substrate. The first gate structure is disposed on the substrate within the MOS transistor region. The first gate structure includes the first dielectric layer, the metal layer, and the semiconductor layer sequentially stacked on the substrate.

Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Abstract: According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes at least one passive component coupled to first and second conductive pads on the upper surface of the substrate. The semiconductor package further includes at least one semiconductor device coupled to a first conductive pad on the lower surface of the substrate. The at least one semiconductor device has a first electrode for electrical and mechanical connection to a conductive pad external to the semiconductor package. The at least one semiconductor device can have a second electrode electrically and mechanically coupled to the first conductive pad on the lower surface of the substrate.

Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Abstract: Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.

Abstract: A semiconductor device comprises: a first transistor in a substrate; a second transistor in said substrate; and a further device in said substrate, wherein the second transistor and the further device are arranged to operate at a second voltage which is higher than a first voltage, wherein the first voltage is the (normal) voltage of operation of the first transistor, and wherein the first transistor is isolated from the second voltage.

Abstract: An ESD protection circuit including an SCR having at least one PNP transistor and at least one NPN transistor such that at least one of the PNP transistor and the NPN transistor having an additional second collector. The circuit further including at least one control circuit coupled to the at least one second collector to control holding voltage of the SCR.

Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

Abstract: It is an object of the present invention to provide a semiconductor apparatus for solving a trade-off between the area, power consumption, noise and accuracy of correction of a variation correction circuit that corrects variations in resistance and threshold voltage, etc. The present invention comprises a multi-value voltage generation circuit shared by a plurality of reading circuits, a multi-value voltage bus that supplies multi-value voltages to the reading circuits and switches that select a voltage suited to variation correction from multi-value voltages, wherein the multi-value voltages are distributed from the multi-value voltage generation circuit to the plurality of reading circuits, the switches select an optimum voltage for correction in the respective reading circuits to thereby correct variations in the elements.

Abstract: In the method a first layer, particularly of amorphous silicon, is deposited on the surface of a substrate with trenches. Part of this surface is covered with a protective layer. The first layer is thereafter maskless removed with a dry etching treatment on the substrate surface while it is kept within the trench.

Abstract: A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.

Abstract: There is provided a semiconductor package that includes a first semiconductor die mounted on a package substrate. The semiconductor package further includes a second semiconductor die mounted on the first semiconductor die and including a thermal sensing and reset protection circuit. The thermal sensing and reset protection circuit is configured to determine a temperature of the first semiconductor die and to provide a reset protection signal to the first semiconductor die when the temperature of the first semiconductor die is substantially equal to a preset temperature so as to protect the first semiconductor die from thermal runaway. The reset protection signal can cause the first semiconductor die to be in a sleep mode or a reset state.

Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Abstract: A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysilicon layer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an amorphous layer (86) is created on the substrate (10) so as to improve the Q factor of the inductor (70), without the need for an additional masking step or adverse impact on the polysilicon layer (30).

Abstract: A semiconductor device is configured that a high-withstand voltage semiconductor device and logic circuits are integrated on a single chip and that a high-withstand voltage high-potential island including the high-potential-side logic circuit is separated using multiple partition walls enclosing therearound. The semiconductor device is provided with a multi-trench separation region having a level shift wire region that is used to connect the high-potential-side logic circuit to the high-potential-side electrode of the high-withstand voltage semiconductor device.

Abstract: The invention includes a laterally double-diffused metal-oxide semiconductor (LDMOS) having a reduced size, a high breakdown voltage, and a low on-state resistance. This is achieved by providing a thick gate oxide on the drain side of the device, which reduces electric field crowding in the off-state to reduce the breakdown voltage and forms an accumulation layer in the drift region to reduce the device resistance in the on-state. A version of the device includes a low voltage version with a thin gate oxide on the source side of the device and a high voltage version of the device includes a thick gate oxide on the source side. The LDMOS may be configured in an LNDMOS having an N type source or an LPDMOS having a P type source. The source of the device is fully aligned under the oxide spacer adjacent the gate to provide a large SOA and to reduce the device leakage.

Abstract: A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.

Abstract: A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.

Abstract: Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

Abstract: A method of forming a circuit includes providing a first substrate; positioning an interconnect region on a surface of the first substrate; providing a second substrate; positioning a device structure on a surface of the second substrate, the device structure including a stack of at least three doped semiconductor material layers; and bonding the device structure to the interconnect region.

Abstract: A semiconductor layer structure includes a donor substrate and a detach region carried by the donor substrate. A device structure is carried by the donor substrate and positioned proximate to the detach region. The device structure includes a stack of crystalline semiconductor layers. The stack of crystalline semiconductor layers includes a pn junction.

Abstract: A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device.

Abstract: A two-terminal capacitive circuit element 100 includes a MOS transistor including a source 126 and drain 127 separated by a body region 131, and a gate 105 separated from the body 129 by a gate insulator layer 110, and a bypass capacitor 125. The gate node (port2; 115) is AC grounded through the bypass capacitor 125 and the source 126 and drain 127 are tied together (port-1; 120). By toggling the transistor on and off using an appropriate gate to body voltage, the capacitance of the capacitive circuit element 100 between port-1 and port-2 significantly changes.

Abstract: In one embodiment of the present invention, provided is a semiconductor device having a silicon substrate provided with a DRAM region containing first transistors and capacitor elements, and with a logic region containing second transistors. A minimum gate length of the second transistors provided in the logic region is smaller than a minimum gate length of the first transistors provided in the DRAM region. One of a cobalt silicide layer and a titanium silicide layer is provided on source/drain regions and on gate electrodes of the first transistors provided in the DRAM region, and a nickel-containing silicide layer is provided on source/drain regions and on gate electrodes of the second transistors provided in the logic region.

Abstract: A semiconductor device includes a device isolation layer disposed in a substrate and defining an active region, a first gate pattern on the active region, a first insulating layer on the substrate and the first gate pattern, a first body region on the first insulating layer, and a first substrate plug extending from the substrate into the first insulating layer, the first substrate plug penetrating the device isolation layer and contacting the substrate under the device isolation layer.

Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: To prevent the potential inversion of a dynamic node attributed to the fact that any wiring line among standard cells as is made of a wiring layer at the same level as that of the dynamic node within a standard cell is laid in adjacency to the dynamic node. In adjacency to a dynamic node 101 within a standard cell, shield wiring lines 102a and 102b which are made of wiring layers at the same level as that of the dynamic node are laid so as to prevent any wiring line among standard cells from passing in adjacency to the dynamic node. The shield wiring lines can be replaced with a shield region or a wiring inhibition region.

Abstract: An ESD protection device for protecting a circuit against electrostatic discharges. The ESD protection device having a series circuit of N diodes, each diode comprising an anode and a cathode. The series circuit being connected between two supply potentials. The diodes being so arranged that a spatial distance between the anode of a first diode and the cathode of an Nth diode of the series circuit is less than a maximum distance between the anode or cathode of a first spatially outer diode of the series circuit and the anode or cathode of a second spatially outer diode of the series circuit.

Abstract: In a semiconductor integrated circuit for a DC—DC converter, an nMOS-type transistor Qn of a CMOS inverter 1c constituting a driver 1 is electrically floated from a substrate 12 through an n-type well region 11. Thus, the nMOS-type transistor Qn is electrically insulated from other transistors such as an npn-type transistor Q1 and an L-pnp-type transistor Q2 constituting a feedback control system 9 through the n-type well region 11. Stable operation is performed with a minute current without producing a malfunction caused by the influence of a parasitic current, even if the drain potential of an nMOS-type transistor is reduced to the ground potential or lower at the time of switching by a driver constituted from a CMOS inverter, to facilitate lower power consumption and higher efficiency, and also to eliminate a constraint on layout design of components.

Abstract: A semiconductor memory device includes a nonvolatile memory section; and a volatile memory section, wherein the nonvolatile memory section includes a nonvolatile memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function for retaining charges.

Abstract: An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.