Abstract: A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).

Abstract: Voltage converters with integrated low power leaker device and associated methods are disclosed herein. In one embodiment, a voltage converter includes a switch configured to convert a first electrical signal into a second electrical signal different than the first electrical signal. The voltage converter also includes a controller operatively coupled to the switch and a leaker device electrically coupled to the controller. The controller is configured to control the on and off gates of the switch, and the leaker device is configured to deliver power to the controller. The leaker device and the switch are formed on a first semiconductor substrate, and the controller is formed on second semiconductor substrate separate from the first semiconductor substrate.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract: The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF).

Abstract: It is an object to suppress deterioration in characteristics of a transistor in a driver cricuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: A semiconductor device has a semiconductor substrate, a pair of diffusion layers formed in a predetermined regions of the semiconductor substrate, a gate insulation film formed on a region of the semiconductor substrate being interposed between the pair of the diffusion layers, a gate electrode formed on the gate insulation film, insulation films formed on the sides of the gate electrode, each of the insulation films being constructed from one or more layers, sidewall spacers formed on the sides of the gate electrode while the insulation films are interposed between the sidewall spacers and the gate electrode, and highly doped diffusion layers formed in the diffusion layers except for the parts under the insulation films and the sidewall spacers.

Abstract: According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A memory comprising at least one memory cell operationally connected to a bit line, a source line and a word line. The memory cell comprises a substrate having a first source contact, a second source contact, and a bit contact between the first source contact and the second source contact, a first transistor gate electrically connecting the first source contact and the bit contact and a second transistor gate electrically connecting the bit contact and the second source contact. The word line electrically connects the first transistor gate to the second transistor gate.

Abstract: A semiconductor device capable of compensating for an electrical characteristic variation of a transistor array is provided. The semiconductor device includes an N-well region and a transistor array spaced from the N-well region and including a plurality of transistors. A characteristic of each of the transistors is adjusted to enable the transistors to have a same electrical characteristic.

Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region.

Abstract: A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used for connecting with a Vss voltage or a Vdd voltage, and a salicide layer disposed on the gates, the source doped regions except those source doped regions used for connecting a Vss voltage and a Vdd voltage and the drain doped regions.

Abstract: A structure of a plurality of thin film transistors wherein a peripheral circuit on a glass substrate of a liquid crystal display panel; and each of polycrystalline silicon thin film 13 of the thin film transistor is formed on the glass substrate; and each of gate electrode 15 is formed on a gate insulation layer, and each of the gate electrode 15 is overhead corresponding to the polycrystalline silicon thin film 13 for a channel; wherein the gate electrode 15 is comprised a pair of projection part 15A and a gate-channel 15B; and wherein the pair of projection part 15A is formed the both sides of the gate-channel 15B in which the side is for along the channel-direction, and wherein the pair of projection part 15A is enlarged for across the channel-direction.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide layer of a refractory metal, an area of DRAM cells and the like into a single semiconductor chip. According to the present invention, a semiconductor device is constituted such that an insulating film having a plurality of layers is used, sidewalls at the gate electrodes are formed by etchingback the insulating film of the plurality of layers or a single layer film in the region where metal silicide layers are formed and in the region where the metal silicide layers are not formed, sidewalls composed of an upper layer insulating film is formed on a lower layer insulating film whose surface is coated or the insulating film of the plurality of layers remain unchanged.

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed.

Abstract: The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide layer of a refractory metal, an area of DRAM cells and the like into a single semiconductor chip. According to the present invention, a semiconductor device is constituted such that an insulating film having a plurality of layers is used, sidewalls at the gate electrodes are formed by etchingback the insulating film of the plurality of layers or a single layer film in the region where metal silicide layers are formed and in the region where the metal silicide layers are not formed, sidewalls composed of an upper layer insulating film is formed on a lower layer insulating film whose surface is coated or the insulating film of the plurality of layers remain unchanged.

Abstract: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between the third terminal (9) and a second terminal (8) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal (9) and the second terminal (8). Given pulse voltages are applied between the first terminal (7) and the third terminal (9) and between the third terminal (9) and the second terminal (8) to reversibly change the resistance values of the first and second variable resistors (5, 6), thereby recording one bit or multiple bits of information.

Abstract: A down converter includes an integrated circuit, which includes a control FET (CF) and a synchronous rectifier FET (SF). The control FET is a lateral double-diffused (LDMOS) FET, and the conductivity-type of the LDMOS FET and the conductivity-type of the substrate are of the same type.

Abstract: A disclosed laminated structure includes a wettability variable layer containing a wettability variable material whose surface energy changes when energy is applied thereto and including at least a high surface energy area having high surface energy and a low surface energy area having low surface energy; and a conductive layer disposed on the high surface energy area. The conductive layer includes a first high surface energy area, a second high surface energy area smaller in width than the first high surface energy area, and a third high surface energy area smaller in width than the second high surface energy area. The first high surface energy area and the second high surface energy area are connected by the third high surface energy area.

Abstract: Methods for manufacturing trench type semiconductor devices containing thermally unstable refill materials are provided. A disposable material is used to fill the trenches and is subsequently replaced by a thermally sensitive refill material after the high temperature processes are performed. Trench type semiconductor devices manufactured according to method embodiments are also provided.

Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

Abstract: A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region.

Abstract: An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide layer contacting a sidewall contact region of the second gate segment and a drain of the first PFET; a third silicide layer contacting a sidewall contact region of the first gate segment and a drain of the second NFET; a fourth silicide layer contacting a first end of the second gate segment, a drain of the first PFET and a drain of a fourth NFET; and a fifth silicide layer contacting a second end of the first gate segment and a drain of a third NFET.

Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.