Abstract: A storage node, a phase change random access memory having an improved structure to improve adhesion of a phase change material layer and methods of fabricating the same are provided. The storage node may include a bottom electrode, a top electrode, a phase change material layer inserted between the bottom electrode and the top electrode, and an adhesion interfacial layer inserted between the bottom electrode and the phase change material layer. The phase change random access memory may include a switching device and the storage node connected to the switching device.

Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.

Abstract: A method of fabricating a sub-feature size pillar structure on an integrated circuit. The process first provides a substrate having formed thereon a phase change layer, an electrode layer and a hard-mask layer. Then there is formed a feature-size hard-mask, by lithographically patterning, etching and stripping a photoresist layer, followed by trimming the hard-mask to a selected sub-feature size, wherein the trimming step is highly selective between the electrode and phase change material layers and the hard-mask. The final steps are trimming the electrode and phase change layers to the size of the hard-mask and removing the hard-mask.

Abstract: A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drain region of the first conduction type formed in the semiconductor layer; a body region of a second conduction type formed in the semiconductor layer between the source region and the drain region, said body region being capable of storing data by accumulating or releasing electric charge; a second insulation layer formed on the body region; a word line formed on the second insulation layer and insulated from the body region by the second insulation layer; and a bit line electrically connected to the drain region, wherein the area of the body region in contact with the first insulation layer is larger than the area thereof in contact with the second insulation layer.

Abstract: An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.

Abstract: Disclosed are a phase-change memory device and its manufacturing method, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing the quantity of current necessary for phase change. The phase-change memory device comprises: a first oxide layer formed on a dielectric interlayer and a bottom electrode on a substrate and having a contact hole for exposing the bottom electrode formed in the first oxide layer; a spacer formed on a side surface of the contact hole; a phase-change layer formed on the spacer and the bottom electrode while forming a shape of another spacer; a second oxide layer filling in the contact hole while exposing an upper portion of the phase-change layer; and a top electrode formed on the first oxide layer while being in contact with the upper portion of the phase-change layer.

Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device includes a heating portion interposed between a transistor and a data storing portion, and a metal interconnection layer connected to the data storing portion. The data storing portion includes a chalcogenide material layer which undergoes a phase change due to heating of the heating portion to store data therein. The heating material layer is disposed under the chalcogenide material layer, and the top surface of the heating material layer is oxidized using a plasma oxidation process to increase a resistance value. Accordingly, the heat capacity necessary for the chalcogenide material layer can be transmitted using a small amount of current, and current used in the semiconductor memory device can be further reduced.

Abstract: In some embodiments, non-volatile memory (NVM) devices are formed on a silicon-on-insulator (SOI) substrate (12) by forming elevated sources and drains (56) in contact with extensions (46) within the top silicon layer (18) of the SOI substrate (12). Buried conductive regions (42) are formed within the top silicon layer (18) below the extensions (46) to mitigate floating body effects that occur when using SOI substrates. In other embodiments, NVM devices are formed using elevated sources and drains (56), extensions (46) and the buried conductive regions (42) in bulk semiconductor substrates. In any embodiment, logic devices may be formed in conjunction with NVM devices, wherein the logic and NVM devices have elevated sources and drains (56), extensions (46) and the buried conductive regions (42).

Abstract: A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.