Input Structure (epo) Patents (Class 257/E29.23)
  • Patent number: 8664036
    Abstract: An oxide semiconductor layer with excellent crystallinity is formed to enable manufacture of transistors with excellent electrical characteristics for practical application of a large display device, a high-performance semiconductor device, etc. By first heat treatment, a first oxide semiconductor layer is crystallized. A second oxide semiconductor layer is formed over the first oxide semiconductor layer. By second heat treatment, an oxide semiconductor layer including a crystal region having the c-axis oriented substantially perpendicular to a surface is efficiently formed and oxygen vacancies are efficiently filled. An oxide insulating layer is formed over and in contact with the oxide semiconductor layer. By third heat treatment, oxygen is supplied again to the oxide semiconductor layer. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hotaka Maruyama, Yoshiaki Oikawa, Katsuaki Tochibayashi
  • Patent number: 7939866
    Abstract: A transistor includes a first electrode on a substrate, wherein the first electrode comprises a bus bar and has first and second first electrode fingers extending therefrom, the fingers being spaced apart to define a channel therebetween. The transistor also includes a second electrode on the substrate having a second electrode finger spaced apart from the first electrode and extending along the channel to define a gate region between the fingers. The gate region comprises a “curved” portion beyond the end of the second electrode finger proximate to the bus bar of the first electrode and a gate electrode extends along the gate region, through the “curved” gate portion. The substrate further comprises an active layer beneath the gate region, characterized in that the active layer extends beyond the end of the second electrode finger beneath the “curved” portion of the gate region.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: May 10, 2011
    Assignee: RFMD (UK) Limited
    Inventor: John Stephen Atherton