Buried Channel Ccd (epo) Patents (Class 257/E29.233)
  • Patent number: 8796748
    Abstract: Transistors, methods of manufacturing thereof, and image sensor circuits are disclosed. In one embodiment, a transistor includes a buried channel disposed in a workpiece, a gate dielectric disposed over the buried channel, and a gate layer disposed over the gate dielectric. The gate layer comprises an I shape in a top view of the transistor.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fredrik Ramberg, Tse-Hua Lu, Tsun-Lai Hsu, Victor Chiang Liang, Chi-Feng Huang, Yu-Lin Wei, Shu Fang Fu
  • Publication number: 20100025738
    Abstract: A charge accumulation region of a first conductivity type is buried in a semiconductor substrate. A charge transfer destination diffusion layer of the first conductivity type is formed on a surface of the semiconductor substrate. A transfer gate electrode is formed on the charge accumulation region, and charge is transferred from the charge accumulation region to the charge transfer destination diffusion layer.
    Type: Application
    Filed: July 27, 2009
    Publication date: February 4, 2010
    Inventor: Yusuke KOHYAMA
  • Patent number: 7544552
    Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: June 9, 2009
    Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
  • Patent number: 7271447
    Abstract: A semiconductor substrate includes a first semiconductor layer that is formed on a semiconductor base substrate, a second semiconductor layer that is formed on the first semiconductor layer and that has an etching selection ratio smaller than that of the first semiconductor layer, a cavity portion that is formed below the second semiconductor layer by removing a portion of the first semiconductor layer, a thermal oxidation film that is formed on the surface of the second semiconductor layer in the cavity portion, and a buried insulating film that is buried in the cavity portion.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 18, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Teruo Takizawa, Kei Kanemoto, Juri Kato, Toshiki Hara
  • Patent number: 7141838
    Abstract: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 28, 2006
    Assignee: Spansion LLC
    Inventor: Michael Brennan