With Delta Or Planar Doped Donor Layer (epo) Patents (Class 257/E29.251)
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Patent number: 9035354Abstract: A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.Type: GrantFiled: September 25, 2009Date of Patent: May 19, 2015Assignee: Cree, Inc.Inventors: Adam William Saxler, Yifeng Wu, Primit Parikh
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Patent number: 9018056Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.Type: GrantFiled: January 31, 2014Date of Patent: April 28, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Charles R. Eddy, Jr., Jennifer K. Hite
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Patent number: 9006791Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.Type: GrantFiled: January 31, 2014Date of Patent: April 14, 2015Assignee: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
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Patent number: 8907378Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.Type: GrantFiled: March 15, 2013Date of Patent: December 9, 2014Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Koon Hoo Teo, Peijie Feng, Rui Ma
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Patent number: 8860088Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. Two slanted field plates are disposed on the two side walls of the combined opening of the opening in a protection layer and the opening in a dielectric cap layer disposed on the second III-V compound layer.Type: GrantFiled: February 23, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Ju Yu, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung
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Patent number: 8710490Abstract: Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.Type: GrantFiled: September 27, 2012Date of Patent: April 29, 2014Assignee: Intel CorporationInventors: Ravi Pillarisetty, Niti Goel, Han Wui Then, Van H. Le, Willy Rachmady, Marko Radosavljevic, Gilbert Dewey, Benjamin Chu-Kung
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Patent number: 8673733Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.Type: GrantFiled: September 27, 2011Date of Patent: March 18, 2014Assignee: SoitecInventors: Mariam Sadaka, Ionut Radu
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Patent number: 8652959Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: February 1, 2013Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Patent number: 8633518Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: December 21, 2012Date of Patent: January 21, 2014Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8558234Abstract: Highly efficient, low energy, low light level imagers and photodetectors are provided. In particular, a novel class of Della-Doped Electron Bombarded Array (DDEBA) photodetectors that will reduce the size, mass, power, complexity, and cost of conventional imaging systems while improving performance by using a thinned imager that is capable of detecting low-energy electrons, has high gain, and is of low noise.Type: GrantFiled: February 11, 2011Date of Patent: October 15, 2013Assignee: California Institute of TechnologyInventors: Shouleh Nikzad, Chris Martin, Michael E. Hoenk
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Patent number: 8525231Abstract: There is provided a semiconductor device and a method of manufacturing the same.Type: GrantFiled: December 10, 2010Date of Patent: September 3, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Ki Yeol Park, Woo Chul Jeon, Young Hwan Park, Jung Hee Lee
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Patent number: 8507329Abstract: A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.Type: GrantFiled: August 22, 2012Date of Patent: August 13, 2013Assignee: Fujitsu LimitedInventors: Toshihide Kikkawa, Kenji Imanishi
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Patent number: 8501508Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: GrantFiled: May 23, 2012Date of Patent: August 6, 2013Assignee: Intel CorporationInventors: Prashant Majhi, Mantu Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Patent number: 8476629Abstract: A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.Type: GrantFiled: September 27, 2011Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Jie Huang, Chi-Yen Lin, Ling-Sung Wang
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Patent number: 8461664Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: May 25, 2011Date of Patent: June 11, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A Papanicolaou
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Patent number: 8384130Abstract: Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, and having an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.Type: GrantFiled: August 3, 2011Date of Patent: February 26, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park
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Patent number: 8344424Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: February 28, 2012Date of Patent: January 1, 2013Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8294181Abstract: A compound semiconductor device is provided with a substrate, an AlN layer formed over the substrate, an AlGaN layer formed over the AlN layer and larger in electron affinity than the AlN layer, another AlGaN layer formed over the AlGaN layer and smaller in electron affinity than the AlGaN layer. Furthermore, there are provided an i-GaN layer formed over the latter AlGaN layer, and an i-AlGaN layer and an n-AlGaN layer formed over the i-GaN layer.Type: GrantFiled: February 1, 2010Date of Patent: October 23, 2012Assignee: Fujitsu LimitedInventors: Toshihide Kikkawa, Kenji Imanishi
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Patent number: 8264004Abstract: A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.Type: GrantFiled: March 1, 2010Date of Patent: September 11, 2012Assignee: Intel CorporationInventors: Been-Yih Jin, Jack T. Kavalieros, Suman Datta, Amlan Majumdar, Robert S. Chau
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Patent number: 8207556Abstract: A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device includes a group III nitride semiconductor supporting base, a GaN based semiconductor region, an active layer, and a GaN semiconductor region. The primary surface of the group III nitride semiconductor supporting base is not any polar plane, and forms a finite angle with a reference plane that is orthogonal to a reference axis extending in the direction of a c-axis of the group III nitride semiconductor. The GaN based semiconductor region, grown on the semipolar primary surface, includes a semiconductor layer of, for example, an n-type GaN based semiconductor doped with silicon. A GaN based semiconductor layer of an oxygen concentration of 5×1016 cm?3 or more provides an active layer, grown on the primary surface, with an excellent crystal quality.Type: GrantFiled: September 23, 2011Date of Patent: June 26, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Kyono, Yusuke Yoshizumi, Yohei Enya, Katsushi Akita, Masaki Ueno, Takamichi Sumitomo, Takao Nakamura
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Patent number: 8193562Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: February 1, 2011Date of Patent: June 5, 2012Assignee: Tansphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Publication number: 20110241017Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recessType: ApplicationFiled: March 31, 2011Publication date: October 6, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
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Patent number: 7915608Abstract: A quantum well device and a method for manufacturing the same are disclosed. In one aspect, the device includes a quantum well region overlying a substrate, a gate region overlying a portion of the quantum well region, a source and drain region adjacent to the gate region. The quantum well region includes a buffer structure overlying the substrate and including semiconductor material having a first band gap, a channel structure overlying the buffer structure including a semiconductor material having a second band gap, and a barrier layer overlying the channel structure and including an un-doped semiconductor material having a third band gap. The first and third band gap are wider than the second band gap. Each of the source and drain region is self-aligned to the gate region and includes a semiconductor material having a doped region and a fourth band gap wider than the second band gap.Type: GrantFiled: May 8, 2009Date of Patent: March 29, 2011Assignees: IMEC, Katholieke Universiteit LeuvenInventors: Geert Hellings, Geert Eneman, Marc Meuris
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Patent number: 7915643Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: September 17, 2007Date of Patent: March 29, 2011Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 7825434Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.Type: GrantFiled: December 29, 2006Date of Patent: November 2, 2010Assignee: Panasonic CorporationInventors: Hiroaki Ueno, Manabu Yanagihara, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
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Patent number: 7777254Abstract: After creating an electron transit layer on a substrate, a baffle is formed on midpart of the surface of the electron transit layer, the surface having a pair of spaced-apart parts left on both sides of the baffle. A semiconducting material different from that of the electron transit layer is deposited on its surface thereby conjointly fabricating an electron supply layer grown continuously on the pair of spaced-apart parts of the electron transit layer surface, and a discontinuous growth layer on the baffle in the midpart of the electron transit layer surface. When no voltage is being impressed to the gate electrode on the discontinuous growth layer, this layer creates a hiatus in the two-dimensional electron gas layer generated along the heterojunction between the electron supply layer and electron transit layer. The hiatus is closed upon voltage application to the gate electrode.Type: GrantFiled: June 9, 2008Date of Patent: August 17, 2010Assignee: Sanken Electric Co., Ltd.Inventor: Ken Sato
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Patent number: 7759142Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.Type: GrantFiled: December 31, 2008Date of Patent: July 20, 2010Assignee: Intel CorporationInventors: Prashant Majhi, Mantu K. Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
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Patent number: 7700975Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.Type: GrantFiled: March 31, 2006Date of Patent: April 20, 2010Assignee: Intel CorporationInventors: Titash Rakshit, Miriam Reshotko
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Patent number: 7683400Abstract: A Si(1-x)MxC material for heterostructures on SiC can be grown by CVD, PVD and MOCVD. SIC doped with a metal such as Al modifies the bandgap and hence the heterostructure. Growth of SiC Si(1-x)MxC heterojunctions using SiC and metal sources permits the fabrication of improved HFMTs (high frequency mobility transistors), HBTs (heterojunction bipolar transistors), and HEMTs (high electron mobility transistors).Type: GrantFiled: June 26, 2006Date of Patent: March 23, 2010Assignee: Northrop Grumman Systems CorporationInventors: Narsingh B. Singh, Brian P. Wagner, David J. Knuteson, Michael E. Aumer, Andre Berghmans, Darren Thomson, David Kahler
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Patent number: 7652311Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.Type: GrantFiled: October 4, 2007Date of Patent: January 26, 2010Assignee: International Rectifier CorporationInventor: Robert Beach
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Patent number: 7612390Abstract: A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.Type: GrantFiled: February 17, 2006Date of Patent: November 3, 2009Assignee: Cree, Inc.Inventors: Adam William Saxler, Yifeng Wu, Primit Parikh
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Patent number: 7569869Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.Type: GrantFiled: March 29, 2007Date of Patent: August 4, 2009Assignee: Intel CorporationInventors: Been-Yih Jin, Robert S. Chau, Suman Datta, Jack T. Kavalieros, Marko Radosavlievic
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Patent number: 7518154Abstract: A substrate system of the kind having a buffer region interposed between a silicon substrate proper and a nitride semiconductor region in order to make up for a difference in linear expansion coefficient therebetween. Electrodes are formed on the nitride semiconductor layer or layers in order to provide HEMTs or MESFETs. The buffer region is a lamination of a multiplicity of buffer layers each comprising a first, a second, and a third buffer sublayer of nitride semiconductors, in that order from the silicon substrate proper toward the nitride semiconductor region. The three sublayers of each buffer layer contain aluminum in varying proportions including zero. The aluminum proportion of the third buffer sublayer is either zero or intermediate that of the first buffer sublayer and that of the second.Type: GrantFiled: November 15, 2004Date of Patent: April 14, 2009Assignee: Sanken Electric Co., Ltd.Inventors: Koji Otsuka, Masataka Yanagihara, Nobuo Kaneko
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Patent number: 7508014Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.Type: GrantFiled: November 16, 2005Date of Patent: March 24, 2009Assignee: Nichia CorporationInventor: Masashi Tanimoto
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Patent number: 7432538Abstract: A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. The channel is formed near the interface between the channel layer and the carrier supply layer or depleted, the carrier supply layer has a band gap energy greater than that of the channel layer, and x in the formula AlxGa1-xN decreases monotonically with an increase in the distance from the interface. The channel layer may be crystalline of gallium nitride. The channel layer may be undoped. X of the formula AlxGa1-xN of the carrier supply layer is greater than or equal to 0.15 and less than or equal to 0.40 at the interface.Type: GrantFiled: September 19, 2006Date of Patent: October 7, 2008Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Kosaki, Koji Hirata
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Publication number: 20080237636Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Been-Yih Jin, Robert S. Chau, Suman Datta, Jack T. Kavalieros, Marko Radosavlievic
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Patent number: 7429747Abstract: A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.Type: GrantFiled: November 16, 2006Date of Patent: September 30, 2008Assignee: Intel CorporationInventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Mark L. Doczy, Robert S. Chau
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Patent number: 7170111Abstract: A nitride-based field effect transistor includes a substrate, a channel layer comprising InAlGaN formed on the substrate, source and drain ohmic contacts in electrical communication with the channel layer, and a gate contact formed on the channel layer. At least one energy barrier opposes movement of carriers away from the channel layer. The energy barrier may comprise an electron source layer in proximity with a hole source layer which generate an associated electric field directed away from the channel. An energy barrier according to some embodiments may provide a built-in potential barrier in excess of about 0.5 eV. Method embodiments are also disclosed.Type: GrantFiled: February 5, 2004Date of Patent: January 30, 2007Assignee: Cree, Inc.Inventor: Adam William Saxler