Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

Abstract: A nitride semiconductor device includes a channel layer, a barrier layer made of AlxInyGa1-x-yN (x>0, x+y?1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.

Abstract: A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

Abstract: A semiconductor component includes at least two functional units which are identical to one another and are wired to one another, the identical functional units each include at least one gate finger, at least one source finger and at least one drain finger; the wiring comprising conductor tracks. A first track connects the gate fingers respectively, a second track connects the source fingers respectively, and a third track connects the drain fingers of the at least two same functional units, respectively.

Abstract: An integrated enhancement/depletion mode high electron mobility transistor (HEMT) includes a substrate, a buffer layer, a first barrier layer, a second barrier layer, a first source, a first drain a first gate, a second source, a second drain, and a second gate. The buffer layer is on the substrate. The first barrier layer is on the buffer layer, and the second barrier layer is on the first barrier layer. The second barrier layer covers a portion of the first barrier layer. The first source, the first drain, and the first gate are on the first barrier layer, and the second source, the second drain, and the second gate are on the second banner layer.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: A nitride semiconductor device includes: a substrate having a first main surface and a second main surface; a first nitride semiconductor layer of a first conductivity type provided above the first main surface; a second nitride semiconductor layer of a second conductivity type provided above the first nitride semiconductor layer; a first opening which penetrates through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer provided above the second nitride semiconductor layer and on an inner surface of the first opening; a gate electrode provided above the electron transport layer and covering the first opening; a source electrode connected to the second nitride semiconductor layer; a drain electrode provided on a second main surface-side of the substrate; and a high-resistance layer provided between the second nitride semiconductor layer and the electron transport layer in the first opening, the high-resistance layer including a nitride semiconductor.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes sequentially forming a first semiconductor layer, a second semiconductor layer and a semiconductor cap layer containing a p-type impurity element on a substrate, forming a dielectric layer having an opening after the forming of the semiconductor cap layer, forming a third semiconductor layer containing a p-type impurity element on the semiconductor cap layer exposed from the opening of the dielectric layer, and forming a gate electrode on the third semiconductor layer.

Abstract: A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith.

Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: A transistor includes a first layer of a first type disposed over a buffer layer and having a first concentration of a first material. A first layer of a second type is disposed over the first layer of the first type, and a second layer of the first type is disposed over the first layer of the second type. The second layer of the first type having a second concentration of a first material that is greater than the first concentration of the first material. A source and a drain are spaced laterally from one another and are disposed over the buffer layer. A gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type.

Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. Two slanted field plates are disposed on the two side walls of the combined opening of the opening in a protection layer and the opening in a dielectric cap layer disposed on the second III-V compound layer.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Abstract: The present invention reduces the dynamic on resistance in the channel layer of a GaN device by etching a void in the nucleation and buffer layers between the gate and the drain. This void and the underside of the device substrate may be plated to form a back gate metal layer. The present invention increases the device breakdown voltage by reducing the electric field strength from the gate to the drain of a HEMT. This electric field strength is reduced by placing a back gate metal layer below the active region of the channel. The back gate metal layer may be in electrical contact with the source or drain.

Abstract: The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication method uses selective decomposition and selective regrowth of the Barrier layer and the Cap layer to engineer the bandgap of a region on a die to form an enhancement mode region. In these regions zero or more devices may be fabricated.

Abstract: A semiconductor device according to an exemplary embodiment comprises a substrate, a middle layer comprising a first semiconductor layer disposed on the substrate and comprising AlxGa1-xN (0?x?1) doped with a first dopant and a second semiconductor layer disposed on the first semiconductor layer and comprising undoped gallium nitride (GaN) and a drive unit disposed on the second semiconductor layer.

Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer formed of non-doped AlXGa1-XN (0?X<1); a second nitride semiconductor layer formed on the first nitride semiconductor layer of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y), and having a smaller lattice constant than that of the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer of a non-doped or n-type nitride semiconductor, and having a lattice constant equal to that of the first nitride semiconductor layer; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer of InWAlZGa1-W-ZN (0<W?1, 0<Z<1); a gate electrode formed in a recess structure having a bottom face which arrives at the third nitride semiconductor layer; and a source electrode and a drain electrode.

Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

Abstract: The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.

Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.

Abstract: A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers.

Abstract: A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain.

Abstract: An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; and a p-type semiconductor layer formed between the electron supply layer and the gate electrode. The p-type semiconductor layer contains, as a p-type impurity, an element same as that being contained in at least either of the electron channel layer and the electron supply layer.

Abstract: Provided is a power device. The power device may include a two-dimensional electron gas (2-DEG) layer in a portion corresponding to a gate electrode pattern since a second nitride layer is further formed on a lower portion of the gate electrode pattern after a first nitride layer is formed and thus, may be capable of performing a normally-OFF operation. Accordingly, the power device may adjust generation of the 2-DEG layer based on a voltage of a gate, and may reduce power consumption. The power device may regrow only the portion corresponding to the gate electrode pattern or may etch a portion excluding the portion corresponding to the gate electrode pattern and thus, a recess process may be omissible, a reproducibility of the power device may be secured, and a manufacturing process may be simplified.

Abstract: A semiconductor device includes: substrate region; a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of the substrate regions; an active area between gate and source placed between the gate electrode and the source electrode; an active area between gate and drain placed between the gate electrode and the drain electrode; an active area placed on the substrate region of the underneath part of the gate electrode, the source electrode, and the drain electrode; and a non-active area placed adjoining the active area, the active area between gate and source, and the active area between gate and drain. Furthermore, width WA1 of the active area between gate and source is wider than width WA2 of the active area between gate and drain. Channel resistance of an active area between source and gate placed between a gate electrode and a source electrode is reduced, and high-frequency performance is provided.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A semiconductor device includes a compound semiconductor layer provided over a substrate, a plurality of source electrodes and a plurality of drain electrodes provided over the compound semiconductor layer, a plurality of first vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of source electrodes, a plurality of second vias each of which is configured to pass through the compound semiconductor layer and be coupled to a corresponding one of the plurality of drain electrodes, a common source wiring line configured to be coupled to the plurality of first vias and be buried in the substrate, and a common drain wiring line configured to be coupled to the plurality of second vias and be buried in the substrate.

Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode.

Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.

Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.

Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Abstract: A semiconductor device includes: a channel layer made of a compound semiconductor; a barrier layer provided above the channel layer and made of a compound semiconductor in which an energy band on a carrier travel side in a junction with respect to the channel layer is farther from an intrinsic Fermi level in the channel layer than in the channel layer; a low-resistance region provided in a surface layer of the barrier layer, in which resistance is kept lower than portions around by containing impurity; a source electrode and a drain electrode connected to the barrier layer at positions sandwiching the low-resistance region; a gate insulating layer provided on the low-resistance region; and a gate electrode provided above the low-resistance region through the gate insulating layer.

Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.