Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.

Abstract: A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.

Abstract: A stage apparatus for a particle-beam apparatus is disclosed. A particle beam apparatus may comprise a conductive object and an object table, the object table being configured to support an object. The object table comprises a table body and a conductive coating, the conductive coating being provided on at least a portion of a surface of the table body. The conductive object is disposed proximate to the conductive coating and the table body is provided with a feature proximate to an edge portion of the conductive coating. Said feature is arranged so as to reduce an electric field strength in the vicinity of the edge portion of the conductive coating when a voltage is applied to both the conductive object and the conductive coating.

Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

Abstract: A method of manufacturing a semiconductor optical device of this disclosure includes the steps of forming an etch stop layer on an InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and forming a semiconductor laminate on the etch stop layer by stacking a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P. Further, an intermediate article of a semiconductor optical device of the present disclosure includes an InP growth substrate; an etch stop layer formed on the InP growth substrate, the etch stop layer having a thickness of 100 nm or less; and a semiconductor laminate formed on the etch stop layer, including a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P stacked one another.

Abstract: A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.

Abstract: A semiconductor device includes: a channel layer not containing Al; a barrier layer above the channel layer containing Al; a recess; and an ohmic electrode in the recess, which is in ohmic contact with a two-dimensional electron gas layer. An Al composition ratio distribution of the barrier layer has a maximum point at a first position. The semiconductor device includes: a first inclined surface of the barrier layer which includes the first position and is in contact with the ohmic electrode; and a second inclined surface of the barrier layer which intersects the first inclined surface on a lower side of the first inclined surface, and is in contact with the ohmic electrode. To the surface of the substrate, an angle of the second inclined surface is smaller than an angle of the first inclined surface. A position of the first intersection line is lower than the first position.

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

Abstract: An HEMT includes a semiconductor body, which includes a semiconductor heterostructure, and a conductive gate region. The gate region includes: a contact region, which is made of a first metal material and contacts the semiconductor body to form a Schottky junction; a barrier region, which is made of a second metal material and is set on the contact region; and a top region, which extends on the barrier region and is made of a third metal material, which has a resistivity lower than the resistivity of the first metal material. The HEMT moreover comprises a dielectric region, which includes at least one front dielectric subregion, which extends over the contact region, delimiting a front opening that gives out onto the contact region; and wherein the barrier region extends into the front opening and over at least part of the front dielectric subregion.

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.

Abstract: A semiconductor device includes a barrier layer, a dielectric layer, a first spacer, a second spacer, and a gate. The dielectric layer is disposed on the barrier layer and defines a first recess. The first spacer is disposed on the barrier layer and within the first recess. The second spacer is disposed on the barrier layer and within the first recess. The first and second spacers are spaced apart from each other by a top surface of a portion of the barrier layer. The top surface of the portion of the barrier layer is recessed. The gate is disposed on the barrier layer, the dielectric layer, and the first and second spacers, in which the gate has a bottom portion located between the first and second spacers and making contact with the top surface of the portion of the barrier layer.

Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, a semiconductor member, and a first insulating member. The semiconductor member includes a first face and a first side face. A third insulating region is between the first face and the third electrode in a second direction. A first insulating region is between the first side face and the third electrode in a first direction. The first side face includes first and second side face portions. The first side face portion is between the first face and the second side face portion in the second direction. At least a first angle between a first plane including the first face and the first side face portion and a second angle between the first plane and the second side face portion is less than 90 degrees. The second angle is different from the first angle.

Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.

Abstract: An enhancement-mode III-V HEMT based on an all-solid-state battery is provided. In which, a second semiconductor layer and a first semiconductor layer are sequentially formed on a substrate, and a heterostructure is formed between the second semiconductor layer and the first semiconductor layer; a source electrode is electrically connected to a drain electrode through a 2DEG generated in the heterostructure; a gate electrode is used to control on-off of the 2DEG in the heterostructure; and an all-solid-state battery is arranged between the source electrode and the gate electrode, is composed of at least one group of battery units connected in series or connected in series and parallel, and is used to deplete the 2DEG in a corresponding region of the heterostructure.

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A carrier channel depleting layer is disposed on the second III-V compound layer. The carrier channel depleting layer is deposited using plasma and a portion of the carrier channel depleting layer is under at least a portion of the gate electrode.

Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.

Abstract: A compound semiconductor device includes an electron transit layer; an electron supply layer formed over the electron transit layer; a first recessed portion and a second recessed portion formed in the electron supply layer; a chemical compound semiconductor layer including impurities that buries the first recessed portion and the second recessed portion and covers over the electron supply layer; a source electrode formed over the chemical compound semiconductor layer which buries the first recessed portion; a drain electrode formed over the chemical compound semiconductor layer which buries the second recessed portion; and a gate electrode formed over the electron supply layer between the source electrode and the drain electrode, wherein, in the chemical compound semiconductor layer, a concentration of impurities included below the source electrode and the drain electrode is higher than a concentration of impurities included near the gate electrode.

Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: A first nitride semiconductor layer contains Ga. The first nitride semiconductor layer is, for example, a GaN layer, an AlGaN layer, or an AlInGaN layer. Then, an aluminum oxide layer has tetra-coordinated Al atoms each surrounded by four O atoms and hexa-coordinated Al atoms each surrounded by six O atoms as Al atoms in the interface region with respect to the first nitride semiconductor layer. The interface region is a region apart, for example, by 1.5 nm or less from the interface with respect to the first nitride semiconductor layer. Then, in the interface region, the tetra-coordinated Al atoms are present by 30 at % or more and less than 50 at % based on the total number of Al atoms.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. Two slanted field plates are disposed on the two side walls of the combined opening of the opening in a protection layer and the opening in a dielectric cap layer disposed on the second III-V compound layer.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.

Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.

Abstract: A semiconductor device according to an exemplary embodiment comprises a substrate, a middle layer comprising a first semiconductor layer disposed on the substrate and comprising AlxGa1-xN (0?x?1) doped with a first dopant and a second semiconductor layer disposed on the first semiconductor layer and comprising undoped gallium nitride (GaN) and a drive unit disposed on the second semiconductor layer.

Abstract: A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: A nitride semiconductor device in which contact resistance between an ohmic electrode and an ohmic recess portion is reduced and a method of manufacturing the nitride semiconductor device are provided. The nitride semiconductor device includes: a first nitride semiconductor layer formed on a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than a bandgap of the first nitride semiconductor layer; an ohmic recess portion formed in at least the second nitride semiconductor layer; and an ohmic electrode provided in contact with the ohmic recess portion. The ohmic recess portion includes a corrugated structure in at least a part of a plane in contact with the ohmic electrode.

Abstract: A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate.

Abstract: A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.

Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

Abstract: Provided is a nitride semiconductor device including: a nitride semiconductor layer over a substrate wherein the nitride semiconductor has a two-dimensional electron gas (2DEG) channel inside; a drain electrode in ohmic contact with the nitride semiconductor layer; a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, and having an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; a dielectric layer formed on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and a gate electrode disposed on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed over a drain-side edge portion of the source electrode with the dielectric layer interposed therebetween, and a manufacturing method thereof.

Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.

Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

Abstract: A normally-off transistor includes a first region of III-V semiconductor material, a second region of III-V semiconductor material on the first region, a third region of III-V semiconductor material on the second region and a gate electrode adjacent at least one sidewall of the third region. The first region provides a channel of the transistor. The second region has a band gap greater than the band gap of the first region and causes a 2-D electron gas (2DEG) in the channel. The second region is interposed between the first region and the third region. The third region provides a gate of the transistor and has a thickness sufficient to deplete the 2DEG in the channel so that the transistor has a positive threshold voltage.

Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Abstract: A semiconductor device including a field effect transistor having a buffer layer subjected to lattice relaxation, a channel layer, and an electron supply layer formed in this order with group-III nitride semiconductors respectively in a growth mode parallel with a [0001] or [000-1] crystallographic axis over a substrate and having a source electrode and a drain electrode, those being coupled electrically to the channel layer, and a gate electrode formed over the electron supply layer, in which, in the buffer layer and the electron supply layer, a layer existing on the group-III atomic plane side of the channel layer has an A-axis length larger than a layer existing on the group-V atomic plane side of the channel layer; and the electron supply layer has a bandgap larger than the channel layer.