Abstract: A MOS transistor having a recessed channel region is provided. A MOS transistor includes a source region and a drain region disposed in an active region of a semiconductor substrate and spaced apart from each other. A gate trench structure is disposed in the active region between the source and drain regions. A gate electrode is disposed in the gate trench structure. A gate dielectric layer is interposed between the gate trench structure and the gate electrode. A semiconductor region is disposed between the gate trench structure and the gate dielectric layer. The semiconductor region is formed of a different material from the active region. A method of fabricating the MOS transistor having a recessed channel region is also provided.

Abstract: A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin

Abstract: An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.

Abstract: This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region.

Abstract: In a semiconductor element (20) including a field effect transistor (90), a schottky electrode (9a) and a plurality of bonding pads (12S, 12G), at least one of the plurality of bonding pads (12S, 12G) is disposed so as to be located above the schottky electrode (9a).

Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Abstract: The transistor comprises a source and a drain separated by a lightly doped intermediate zone. The intermediate zone forms first and second junctions respectively with the source and with the drain. The transistor comprises a first gate to generate an electric field in the intermediate zone, on the same side as the first junction, and a second gate to generate an electric field in the intermediate zone, on the same side as the second junction.

Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Abstract: Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.

Abstract: A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.

Abstract: In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

Abstract: The method of forming a semiconductor structure in a substrate comprises, forming a first trench with a first width We and a second trench with a second width Wc, wherein the first width We is larger than the second width Wc, depositing a protection material, lining the first trench, covering the substrate surface and filling the second trench and removing partially the protection material, wherein a lower portion of the second trench remains filled with the protection material.

Abstract: Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode.

Abstract: A semiconductor device, including a first semiconductor layer of the first conductivity type having a plurality of trenches formed therein. A second semiconductor layer of the second conductivity type composed of an epitaxial layer is buried in the trenches in the first semiconductor layer. The trench has surface orientations including a surface orientation of a sidewall at an upper stage made slower in epitaxial growth speed than a surface orientation of a sidewall at a lower stage.

Abstract: A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).

Abstract: A component arrangement. One embodiment includes a power semiconductor component having a drift zone arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. A capacitive storage arrangement is coupled to the drift control zone. A charging circuit is coupled between the first component zone and the capacitive storage arrangement.

Abstract: A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first conductivity type, second semiconductor layers of the first conductivity type and third semiconductor layers of a second conductivity type, which are formed on the first semiconductor layer, have stripe shapes extending in a first horizontal direction, and are alternately arranged along a second horizontal direction orthogonal to the first horizontal direction, a fourth semiconductor layer of the second conductivity type, selectively formed on a surface of one of the third semiconductor layers, a fifth semiconductor layer of the first conductivity type, selectively formed on a surface of the fourth semiconductor layer, and formed into a stripe shape extending in the first horizontal direction without being formed into a stripe shape extending in the second horizontal direction, and a control electrode formed on the second, third, fourth, and fifth semiconductor layers via an insulat

Abstract: A semiconductor device includes: a substrate; a first junction region and a second junction region formed separately from each other in the substrate; an etch barrier layer formed in the substrate underneath the first junction region; and a plurality of recess channels formed in the substrate between the first junction region and the second junction region.

Abstract: In a chip containing high-voltage device with a semiconductor substrate of a first conductivity type, a method of implementing low-voltage power supply is provided, wherein the electrical potential of an isolated region of a second conductivity type in a surface portion is used as one output terminal or as a voltage by which a transistor is controlled to provide output current for a low-voltage power supply. The other output terminal could be either terminal of the two that apply high voltage to high-voltage device or could be a floating terminal. Using this method, a low-voltage power supply can be implemented not only for the low-voltage integrated circuit (I) in a power IC containing one high-voltage device, but also for the low-voltage integrated circuit in a power IC having totem-pole connection or CMOS connection. As there is no need to implement depletion mode device in the chip, the fabrication cost is reduced.

Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance. The device combines a static induction transistor structure with an insulated gate field effect transistor structure. The advantages of both the SIT structure and the insulated gate field effect transistor structure are obtained. The structures are formed on the same SiC semiconductor substrate, with the MOSFET structure above the SIT structure. The SIT structure includes a p+ gate region in an n-type drift layer on an n+ SiC semiconductor substrate, and an n+ first source region on the surface of the drift layer. The MOSFET structure includes a p-well region on the surface of the first source region, a second source region formed in the p-well region, and a MOS gate structure formed in a trench extending from the second source region to the first source region. The p+ gate region and a source electrode are conductively connected.

Abstract: A semiconductor structure and associated method of formation. The semiconductor structure includes a semiconductor substrate, a first doped transistor region of a first transistor and a first doped Source/Drain portion of a second transistor on the semiconductor substrate, a second gate dielectric layer and a second gate electrode region of the second transistor on the semiconductor substrate, a first gate dielectric layer and a first gate electrode region of the first transistor on the semiconductor substrate, and a second doped transistor region of the first transistor and a second doped Source/Drain portion of the second transistor on the semiconductor substrate. The first and second gate dielectric layers are sandwiched between and electrically insulate the semiconductor substrate from the first and second gate electrode regions, respectively. The first and second gate electrode regions are totally above and totally below, respectively, the top substrate surface.

Abstract: This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench.

Abstract: Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.

Abstract: A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

Abstract: In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.

Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.

Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

Abstract: A method for producing a buried n-doped semiconductor zone in a semiconductor body. In one embodiment, the method includes producing an oxygen concentration at least in the region to be doped in the semiconductor body. The semiconductor body is irradiated via one side with nondoping particles for producing defects in the region to be doped. A thermal process is carried out. The invention additionally relates to a semiconductor component with a field stop zone.

Abstract: A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.

Abstract: Disclosed herein is a semiconductor device including: a main body transistor region; and an electrostatic discharge protection element region, wherein the main body transistor region includes, a drain region; a drift region; body regions; a gate insulating film; gate electrodes; source regions; channel regions; and potential extraction regions, and the electrostatic discharge protection element region includes, the body regions; the gate insulating film; the gate electrodes; source regions and drain regions; and potential extraction regions, and a gate length in the electrostatic discharge protection element region is equal to or less than twice a channel length in the main body transistor region.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate.

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer, an insulation layer and a second semiconductor layer, which are stacked in this order; a LDMOS transistor disposed on the first semiconductor layer; and a region having a dielectric constant, which is lower than that of the first or second semiconductor layer. The region contacts the insulation layer, and the region is disposed between a source and a drain of the LDMOS transistor. The device has high withstand voltage in a direction perpendicular to the substrate.

Abstract: A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

Abstract: A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

Abstract: A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.

Abstract: To provide a semiconductor device capable of reducing a gate capacitance, and preventing breakdown of a gate oxide film if a large amount of current flows. A semiconductor device according to an embodiment of the present invention includes: an epitaxial layer; a channel region formed on the epitaxial layer; a trench extending from a surface of the channel region to the epitaxial layer; a gate oxide film that covers an inner surface of the trench; a gate electrode filled into the trench; and a buried insulating film formed below the gate electrode and away from the gate oxide film.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: The invention relates to a semiconductor component, which comprises a semiconductor body having a first and a second terminal zone of a first conduction type (n), a channel zone of a second conduction type (p), which is short circuited with the second terminal zone, a drift zone of the first conduction type (n) with weaker doping than the terminal zones, which drift zone is formed between the channel zone and the first terminal zone, the channel zone being formed between the drift zone and the second terminal zone, a control electrode, formed so that it is insulated from the channel zone, for controlling a conductive channel in the channel zone between the second terminal zone and the drift zone, and is distinguished in that a field stop zone of the first conduction type (n) is formed between the first terminal zone and the drift zone, the field stop zone having heavier doping than the drift zone and weaker doping than the first terminal zone, the maximum doping of the field stop zone being at most a factor o

Abstract: An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.