Abstract: The present invention discloses a high-speed flat panel display with a long lifetime, wherein thin film transistors in a pixel array portion in which a plurality of pixels are arranged and a driving circuit portion for driving the pixels of the pixel array portion, have different resistance values than each other or have different geometric structures than each other. The flat panel display comprises a pixel array portion where a plurality of pixels are arranged, and a driving circuit portion for driving the pixels of the pixel array portion. The thin film transistors in the pixel array portion and the driving circuit portion have different resistance values in their gate regions or drain regions than each other, or have different geometric structures than each other. One of the thin film transistors in the pixel array portion and the thin film transistors in the driving circuit has zigzag shape in its gate region or drain region or has an offset region.

Abstract: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region. A field oxide layer is formed on the substrate around the active region in such a manner that it has a surface lower than the upper surface of the active region including the groove. A pair of gates are placed along one and the other ends of groove across the upper surface of the active region while overlapping the stepped portion of the active region. The transistor has the structure of a step-gated asymmetry transistor when seen in a sectional view taken in a first direction, as well as that of a fin transistor when seen in a sectional view taken in a second direction, which is perpendicular to the first direction.

Abstract: The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.

Abstract: An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

Abstract: The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.

Abstract: Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a groove formed in the active region. A field oxide layer is formed on the substrate around the active region in such a manner that it has a surface lower than the upper surface of the active region including the groove. A pair of gates are placed along one and the other ends of groove across the upper surface of the active region while overlapping the stepped portion of the active region. The transistor has the structure of a step-gated asymmetry transistor when seen in a sectional view taken in a first direction, as well as that of a fin transistor when seen in a sectional view taken in a second direction, which is perpendicular to the first direction.

Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.

Abstract: An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

Abstract: Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.

Abstract: There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix.

Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.

Abstract: The objectives of the present invention are achieving TFTs having a small off current and TFT structures optimal for the driving conditions of a pixel portion and driver circuits, and providing a technique of making the differently structured TFTs without increasing the number of manufacturing steps and the production costs. A semiconductor device has a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The semiconductor layer contains a channel forming region, a region containing a first concentration impurity element, a region containing a second concentration impurity element, and a region containing a third concentration impurity element. The gate electrode is formed by laminating an electrode (A) and an electrode (B).