Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A display substrate is provided, including: a base substrate; a display area, and a peripheral area surrounding the display area on the base substrate, where a dummy pixel unit and a dummy data line are located in the peripheral area. The dummy pixel unit includes a thin film transistor including a first electrode and a second electrode. The first electrode is one of a source electrode and a drain electrode and is electrically connected to the dummy data line, and the second electrode is another of the source electrode and the drain electrode and includes a first portion and a second portion separated by a first opening. A display panel including the display substrate and an electronic device including the display substrate or the display panel are further provided.

Abstract: An internal combustion engine, in particular, a diesel internal combustion engine, including a cylinder crankcase (1), at least one oil return collection groove (2), at least one oil drain (3), in which depressurized oil (4) discharges in the direction of the oil pan, following gravity, and at least one cylinder (5) is provided.

Abstract: A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

Abstract: An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

Abstract: A fingerprint acquisition apparatus includes a plurality of photoelectric conversion units and a first shading pattern. The first shading pattern includes at least one first shading block including a first opening, and an orthographic projection of the first opening in the first shading block on the base substrate is within an orthographic projection of a target photoelectric conversion unit corresponding to the first shading block on the base substrate.

Abstract: An active matrix substrate includes a thin film transistor that includes a gate electrode, a first inorganic insulating film that covers the gate electrode, a second inorganic insulating film that is disposed on the first inorganic insulating film and that has an opening overlapping the gate electrode, a source electrode and a drain electrode disposed on the second inorganic insulating film, and a semiconductor layer that overlaps the gate electrode in an opening of the first inorganic insulating film and that covers the source electrode and the drain electrode. Regarding a surface of the first inorganic insulating film in a first region overlapping the opening of the first inorganic insulating film and a surface in a second region other than the first region, the surfaces being arranged nearer to the second inorganic insulating film, the surface in the first region is lower than the surface in the second region.

Abstract: A structure of a protruding gate transistor is disclosed. The protruding gate transistor comprising a substrate, a source region, a drain region, a channel extension anchor, a channel layer, and gate structure. The gate structure comprising a gate insulator layer, and a gate conductor layer. The channel layer is formed to be protruding from the substrate to extend the length of the channel of the protruding gate transistor and alleviate from channel length modulation.

Abstract: An organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes an organic light-emitting device in which a pixel electrode, an intermediate layer that includes an emissive layer, and a cathode electrode are sequentially stacked. The cathode contact unit includes a cathode bus line that is formed on the same layer as the pixel electrode and contacts the cathode electrode, a first auxiliary electrode that is formed on the cathode bus line along an edge area of the cathode bus line, and a second auxiliary electrode that contacts the first auxiliary electrode.

Abstract: A thin-film semiconductor device according to the present disclosure includes: a substrate; a gate electrode formed above the substrate; a gate insulating film formed on the gate electrode; a channel layer that is formed of a polycrystalline semiconductor layer on the gate insulating film; an amorphous semiconductor layer formed on the channel layer and having a projecting shape in a surface; and a source electrode and a drain electrode that are formed above the amorphous semiconductor layer, and a first portion included in the amorphous semiconductor layer and located closer to the channel layer has a resistivity lower than a resistivity of a second portion included in the amorphous semiconductor layer and located closer to the source and drain electrodes.

Abstract: An organic semiconductor device includes a carrier, a source, a drain, an organic semiconductor single-crystalline channel layer, an organic insulation layer and a gate. The source and the drain are disposed on an upper surface of the carrier. The source and the drain are disposed in parallel and a portion of the carrier is exposed between the source and the drain. The organic semiconductor single-crystalline channel layer is disposed on the upper surface of the carrier and covers a portion of the source, a portion of the drain and the portion of the carrier exposed by the source and the drain. The organic insulation layer covers the carrier, the source, the drain and the organic semiconductor single-crystalline channel layer. The gate is disposed on the organic insulation layer and corresponds to a position of the portion of the carrier exposed by the source and the drain.

Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.

Abstract: A distance (d1) from an edge of a first region (R) at places (D) where branch electrodes (4b) extending, which branch off from an electrode line (4a) of a second source/drain electrode (4), start to overlap with a first region (R) to the electrode line (4a) is 5 ?m or more. This realizes a TFT including a comb-shaped source/drain structure that enables easy repair of a source-drain leakage.

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

Abstract: There are provided a transistor and a radiation imaging device in which a shift in a threshold voltage due to radiation exposure may be suppressed. The transistor includes a first gate electrode, a first gate insulator, a semiconductor layer, a second gate insulator, and a second gate electrode in this order on a substrate. Each of the first and second gate insulators includes one or a plurality of silicon compound films having oxygen, and a total sum of thicknesses of the silicon compound films is 65 nm or less.

Abstract: Methods of anodizing aluminum using a hard mask and related embodiments of semiconductor devices are disclosed herein. Other methods and related embodiments are also disclosed herein.

Abstract: A display device having the high aperture ratio and a storage capacitor with high capacitance is to be obtained. The present invention relates to a display device and a manufacturing method thereof. The display device includes a thin film transistor which includes a gate electrode, a gate insulating film, a first semiconductor layer, a channel protective film, a second semiconductor having conductivity which is divided into a source region and a drain region, and a source electrode and a drain electrode; a third insulating layer formed over the second conductive film; a pixel electrode formed over the third insulating layer, which is connected to one of the source electrode and the drain electrode; and a storage capacitor formed in a region where a capacitor wiring over the first insulating layer and the pixel electrode are overlapped with the third insulating layer over the capacitor wiring interposed therebetween.

Abstract: One object of the present invention is reduction of off current of a thin film transistor. Another object of the present invention is improvement of electric characteristics of the thin film transistor. Further, another object of the present invention is improvement of image quality of the display device including the thin film transistor. The thin film transistor includes a semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at. % or a conductive film which is provided over a gate electrode with the gate insulating film interposed therebetween and which is provided in an inner region of the gate electrode so as not to overlap with an end portion of the gate electrode, a film covering at least a side surface of the semiconductor film containing germanium at a concentration greater than or equal to 5 at. % and less than or equal to 100 at.

Abstract: A method for forming a thin film transistor includes steps of forming a first wiring layer over a first electrode layer and forming a second wiring layer over a second electrode layer, wherein the first electrode layer extends beyond an end portion of the first wiring layer, the second electrode layer extends beyond an end portion of the second wiring layer, and a semiconductor layer is formed so as to be electrically connected to a side face and a top face of the first electrode layer and a side face and a top face of the second electrode layer.

Abstract: A thin film transistor having favorable electric characteristics with high productively is provided. The thin film transistor includes a gate insulating layer covering a gate electrode, a semiconductor layer in contact with the gate insulating layer, an impurity semiconductor layer which is in contact with part of the semiconductor layer and functions as a source region and a drain region, and a wiring in contact with the impurity semiconductor layer. The semiconductor layer includes a microcrystalline semiconductor region having a concave-convex shape, which is formed on the gate insulating layer side, and an amorphous semiconductor region in contact with the microcrystalline semiconductor region. A barrier region is provided between the semiconductor layer and the wiring.

Abstract: A crystal silicon film forming method according to the present invention includes: forming a metal film; forming an insulating film on the metal film, and forming a crystal silicon film made of polycrystal Si on the insulating film. In the forming of an insulating film, the insulating film is formed within a film thickness range of 160 nm to 190 nm. The forming of a crystal silicon film includes forming an amorphous silicon film made of a-Si on the insulating film, within a film thickness range of 30 nm to 45 nm, and forming the crystal silicon film from the amorphous silicon film by irradiating the amorphous silicon film with a light of a green laser.

Abstract: According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor.

Abstract: A flat panel display device is disclosed. In one embodiment, the flat panel display device includes i) a semiconductor layer including a channel region and a groove, wherein the channel region electrically connects a source electrode and a drain electrode, and the groove is configured to separate the channel region from adjacent thin film transistors and ii) a stop layer formed below at least a portion of the semiconductor layer. According to one embodiment of the invention, a semiconductor layer can be easily patterned without using a dry or wet etching technique such as photolithography.

Abstract: To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: Disclosed is a method of forming array substrates having a peripheral wiring area and a display area. The method is processed by only three lithography processes with two multi-tone photomasks and one general photomask. In the peripheral wiring area, the top conductive line directly contacts the bottom conductive line without any other conductive layer. The conventional lift-off process is eliminated, thereby preventing a material (not dissolved by a stripper) from suspending in the stripper or remaining on the array substrate surface.

Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.

Abstract: The invention relates to a process for preparing an electronic device using a protection layer, and to improved electronic devices prepared by this process, in particular organic field effect transistors (OFETs).

Abstract: A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.

Abstract: A display device including an inverter circuit and a switch is provided. The inverter circuit includes a first thin film transistor and a second thin film transistor which have the same conductivity type. The first thin film transistor and the second thin film transistor each include: a gate insulating layer in contact with a gate electrode; a microcrystalline semiconductor layer in contact with the gate insulating layer; a mixed layer in contact with the microcrystalline semiconductor layer; a layer which includes an amorphous semiconductor and is in contact with the mixed layer; and a wiring. A conical or pyramidal microcrystalline semiconductor region and an amorphous semiconductor region filling a space except the conical or pyramidal microcrystalline semiconductor region are included in the mixed layer.

Abstract: An array substrate for a display device and its fabrication method are disclosed. The array substrate for a display device includes: a gate wiring and a gate electrode connected to the wiring formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer and a barrier metal layer stacked with the gate insulating layer interposed therebetween on the gate electrode; a data wiring formed on the barrier metal layer and source and electrodes connected to the data wiring; a passivation film formed on the source and drain electrodes and the data wiring and having a contact hole exposing a portion of the drain electrode, the barrier metal layer and the active layer; and a pixel electrode formed on the passivation film and being in contact with the drain electrode and the barrier metal layer including the active layer.

Abstract: An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: A thin film transistor includes a substrate; a gate electrode on the substrate; a gate insulating layer covering the gate electrode; a semiconductor layer corresponding to the gate electrode on the gate insulating layer; a protective layer covering the semiconductor layer and the gate insulating layer and having a source contact hole and a drain contact hole exposing a portion of the semiconductor layer; and a source electrode and a drain electrode on the protective layer and coupled to the semiconductor layer through the source contact hole and the drain contact hole, respectively, wherein the semiconductor layer has a source offset groove at a portion corresponding to the source contact hole of the protective layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Abstract: A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon.

Abstract: Disclosed is a method that includes: forming a gate electrode on a substrate, then forming an insulation layer so as to completely cover the gate electrode, thereafter forming a semiconductor layer on the insulation layer, and then forming a crystallization-inducing metal layer on the semiconductor layer; removing the part of at least the crystallization-inducing metal layer that is over a channel region of the semiconductor layer; forming source and drain electrodes at a location which is over source and drain regions respectively located at opposite sides with respect to the channel region of the semiconductor layer and is above the crystallization-inducing metal layer; and heating the crystallization-inducing metal layer so as to form a silicide layer of a crystallization-inducing metal.

Abstract: Provided is an image display device including thin film transistors on a substrate, including: gate lines and drain lines intersecting the gate lines, each thin film transistor having, in a channel region, a laminate structure in which a gate electrode, a gate insulating film, and a semiconductor layer are laminated in the stated order from the substrate side; and a pair of removal regions in which parts of the gate insulating film are removed, which are formed on both sides of the gate electrode and formed in a channel width direction of the channel region, in which when W represents a width of the gate electrode in the channel width direction of the channel region, and R represents a width of the gate insulating film in the channel width direction, which is sandwiched between the pair of removal regions, R?W is satisfied.

Abstract: Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed pattern that is formed in a pattern corresponding to that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; a trench type guide portion having a trench type contact window in which an upper portion of the seed pattern is exposed; the gate electrode that is formed by electrodepositing copper on a trench of the exposed seed pattern; a gate insulation film formed on the upper portions of the gate electrode and the trench type guide portion, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film.

Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate including a silicon layer on the substrate surface is provided. A metal layer is formed on the silicon layer. A first dielectric layer is formed on the metal layer and exposed regions of the substrate surface. The metal layer and the silicon layer are treated, and the metal layer reacts with the silicon layer to form a silicide layer and a gap between the silicide layer and the dielectric layer. An amorphous silicon layer is formed on the first dielectric layer. The amorphous silicon layer is heated and cooled. The amorphous silicon layer overlying the substrate surface cools at a faster rate than the amorphous silicon layer overlying the gap.

Abstract: This thin-film transistor includes adhesive strength enhancing films between a barrier film and electrode films. Each of the adhesive strength enhancing film is composed of two zones including (a) a pure copper zone that is formed on the electrode film side, and (b) a component concentrated zone that is formed in an interface portion contact with the barrier film, and that includes Cu, Ca, oxygen, and Si as constituents. In concentration distributions of Ca and oxygen in a thickness direction of the component concentrated zone, a maximum content of Ca of a Ca-containing peak is in a range of 5 to 20 at %, and a maximum content of oxygen of an oxygen-containing peak is in a range of 30 to 50 at %, respectively.

Abstract: According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor.

Abstract: A liquid crystal display (LCD) includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; an active pattern formed as an island on the gate electrode and having a width smaller than the gate electrode; an insulation film formed on the first substrate and having first and second contact holes exposing source and drain regions of the active pattern, respectively; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the first and second contact holes; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region; an etch stopper positioned between the source and drain electrodes and formed as an insulation film; a pixel electrode electrically connected with the drain electrode; and a second substrate attached with the first substrate in a facing ma

Abstract: A thin film transistor and a press sensing device using the thin film transistor are disclosed. The thin film transistor, comprises a source electrode; a drain electrode spaced from the source electrode; a semiconductor layer electrically connected with the source electrode and the drain electrode, a channel defined in the semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode electrically insulated from the semiconductor layer; and an insulative layer configured for insulating the source electrode, the drain electrode, and the semiconductor layer from each other, wherein the insulative layer is made of a polymeric material with an elastic modulus ranged from about 0.1 megapascal (MPa) to about 10 MPa.

Abstract: The invention provides a manufacturing method of a substrate having a film pattern including an insulating film, a semiconductor film, a conductive film and the like by simple steps, and also a manufacturing method of a semiconductor device which is low in cost with high throughput and yield. According to the invention, after forming a first protective film which has low wettability on a substrate, a material which has high wettability is applied or discharged on an outer edge of a first mask pattern, thereby a film pattern and a substrate having the film pattern are formed.

Abstract: A substrate; a gate electrode formed above the substrate; a gate insulating film formed above the gate electrode; a crystalline silicon semiconductor layer formed above the gate insulating film; an amorphous silicon semiconductor layer formed above the crystalline silicon semiconductor layer; an organic protective film made of an organic material and formed above the amorphous silicon semiconductor layer; and a source electrode and a drain electrode formed above the amorphous silicon semiconductor layer interposing the organic protective film are included, and a charge density of the negative carriers in the amorphous silicon semiconductor layer is at least 3×1011 cm?2.