Static Induction Type (i.e., Sit Device) (epo) Patents (Class 257/E31.072)
  • Patent number: 7535039
    Abstract: A dual gate power switch comprised of a vertical arrangement of a normally off SIT (static induction transistor) in series with a normally on SIT in a monolithic semiconductor structure. The structure includes a first pillar having at the base thereof laterally extending shoulder portions having sections of a first gate for controlling the normally off SIT. The structure includes a second pillar, of a width greater than the first pillar and which also has laterally extending shoulder portions having sections of a second gate for controlling the normally on SIT. Contacts are provided for SIT operation.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 19, 2009
    Assignee: Northrop Grumman Corp
    Inventors: Eric J. Stewart, Stephen Van Campen, Rowland C. Clarke
  • Patent number: 7439563
    Abstract: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: October 21, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Hatakeyama, Takashi Shinohe
  • Patent number: 7385231
    Abstract: A method of producing a porous thin-film-deposition substrate, which has the steps of: placing onto a substrate that has an electrostatic charge on its surface, fine particles with a surface electrostatic charge opposite to the electrostatic charge of the substrate surface, depositing a thin film on the fine-particle-placed substrate, and then removing the fine particles to form fine pores in the thin film; further, a method of producing an electron emitting element, which has the steps of: adding a catalyst metal on a substrate, placing fine particles onto the catalyst-added substrate, depositing a thin film on the fine-particle-placed substrate, then removing the fine particles to form fine pores in the film, and growing needle-shaped conductors on the catalyst metal that is exposed on a bottom face of the fine pore.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: June 10, 2008
    Assignee: FujifilmCorporation
    Inventors: Kiyoshi Fujimoto, Masakazu Nakamura
  • Patent number: 7132677
    Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 7, 2006
    Assignee: Dongguk University
    Inventors: Hwa-Mok Kim, Tae-Won Kang, Kwan-Soo Chung