Abstract: A hybrid MOS or CMOS image sensor. The sensor includes photon-sensing elements comprised of an array of photo-sensing regions deposited in the form of separate islands on or in a substrate. Pixel circuitry is created on and/or in the substrate at or near the edge of or beneath the photon-sensing elements. The photo-sensing elements may be comprised of multiple photo-sensing semiconductor layers or be created in a single photon-sensing semiconductor layer. Special circuitry is provided to keep the potential across the pixel photon-sensing element at or near zero volts to minimize or eliminate dark current. The potential difference is preferably less than 1.0 volt. The circuitry also keeps the small potential difference across the photodiodes constant or approximately constant throughout the charge collection cycle.

Abstract: An image sensor includes a plurality of unit pixels arranged in an array. Each unit pixel includes a plurality of sub-pixels configured to be irradiated by light having the same wavelength. Each sub-pixel includes a plurality of floating body transistors. Each floating body transistor includes a source region, a drain region, a floating body region between the source region and the drain region, and a gate electrode formed on the floating body region.

Abstract: The present invention provides an electromagnetic wave detecting element that can suppress occurrence of cracking at a substrate peripheral portion, and occurrence of breakage of lead-out wires. An interlayer insulating film is formed so as to cover TFT switches on a substrate. An interlayer insulating film is formed so as to cover semiconductor layer of sensor portions that generate charges due to electromagnetic waves that are an object of detection being irradiated, and cover a region on the substrate where the interlayer insulating film is formed.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.

Abstract: A semiconductor device having a substrate that contains an insulating layer and a semiconductor layer provided on the insulating layer. The semiconductor also has an optical waveguide that is formed along a predetermined path. This optical waveguide is formed by making the semiconductor layer non-uniformed in thickness thereof. The semiconductor further has a photoreceptor having MISFET containing a floating channel body that is formed on a position of the semiconductor layer in which electric field of light guided inside the optical waveguide exists and a gate for forming channel formed on a front surface side of the channel body.

Abstract: A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.

Abstract: A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.

Abstract: The invention concerns a device for detecting and storing electromagnetic beams, an imager incorporating same, a method for making said device and use thereof. The inventive device comprises a field-effect phototransistor including: two source and drain contact electrodes, an electrical conduction unit which is connected to the two contact electrodes and which is coated with a photosensitive polymeric coating capable of absorbing the beams, of detecting, of generating in response the loads detected by said unit and of storing said loads, and a gate electrode which is capable of controlling the electric current in the unit as well as spatially distributing the loads in said coating and which is separated from said unit by a gate dielectric.

Abstract: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection and readout circuitry over a first substrate, a metal layer over the metal interconnection, and an image sensing device electrically connected to the metal layer. According to embodiments, an electric field may not be generated on and/or over an Si surface. This may contribute to a reduction in a dark current of a 3D integrated CMOS image sensor.

Abstract: An image sensor and manufacturing method thereof are provided. The image sensor can include a gate, a channel region, a first p-type doped region, a second p-type doped region, an n-type doped region, and a floating diffusion region. The gate can be disposed on a semiconductor substrate, and the channel region can be disposed in the semiconductor substrate under the gate. The first p-type doped region can be disposed at a side of the gate and can be adjacent to the channel region. The second p-type doped region can be disposed under the first p-type doped region and spaced apart from the gate. The n-type doped region can be disposed under the first and second p-type doped regions, and the floating diffusion region can be disposed at another side of the gate.

Abstract: Disclosed is a solid-state imaging device which includes a plurality of pixels in an arrangement, each of the pixels including a photoelectric conversion element, pixel transistors including a transfer transistor, and a floating diffusion region, in which the channel width of transfer gate of the transfer transistor is formed to be larger on a side of the floating diffusion region than on a side of the photoelectric conversion element.

Abstract: A sidewall film 121 in a digital portion has a multilayer structure including at least an offset sidewall film 107b located inside. An extension diffusion layer 110 is formed adjacent to a source/drain diffusion region 111 through the offset sidewall film 107b and a gate electrode 102 as a mask. Thus, an operation speed of the digital portion can be increased with a manufacturing process controlled. For a pixel portion, an antireflection film 122 of a laminate structure is formed simultaneously with formation of the sidewall film 121. Thus, the antireflection film thickness can be optimized with the manufacturing process controlled. As a result, a high sensitive MOS solid-state image device can be provided.

Abstract: An image sensor and fabricating method thereof are disclosed by which damage to a protective layer can be prevented in a manner of reducing thermal stress of an uppermost metal line in performing thermal treatment for enhancing the dark characteristic. Such damage can be prevented by forming a poly layer pattern in an insulating interlayer on at least one side of the uppermost layer metal line.

Abstract: An epitaxially layered structure with gate voltage bias supply circuit element for improvement in performance for semiconductor field effect transistor (FET) devices utilizes a structure comprised of a substrate, a first layer semiconductor film of either an n-type or a p-type grown epitaxially on the substrate, with the possibility of a buffer layer between the substrate and first layer film, an active semiconductor layer grown epitaxially on the first semiconductor layer with the conductivity type of the active layer being opposite that of the first semiconductor layer, with the active layer having a gate region and a drain region and a source region with electrical contacts to gate, drain and source regions sufficient to form a FET, an electrical contact on either the substrate or the first semiconductor layer, and a gate voltage bias supply circuit element electrically connected to gate contact and to substrate or first semiconductor layer with voltage polarity and magnitude sufficient to increase device

Abstract: A solid-state imaging device of the present invention includes: a semiconductor substrate including a first region of a first conductivity type; a signal accumulation region of a second conductivity type formed within the first region; a gate electrode formed above the first region; a drain region of a second conductivity type formed on the first region; an isolation region having insulation properties, which is formed to surround a region where the signal accumulation region, the gate electrode, and the drain region are formed; a first conductivity type dopant doping region formed in contact with a side face and a bottom face of the isolation region, the first conductivity type dopant doping region having a higher dopant concentration than the first region; and a second conductivity type dopant doping region formed in the first is region, under an end of the gate electrode in a gate width direction.

Abstract: A light sensor includes an intrinsic layer, a first ion doping area disposed one side of the intrinsic layer, a second ion doping area disposed at the other side of the intrinsic layer, an oxide insulating layer on the intrinsic layer, and a gate metal on the oxide insulating layer. The first and second ion doping areas have the same P type or N type doped ions. The intrinsic layer further includes a first light sensing region close to the first ion doping area. The first light sensing region is used for generating electron-hole pairs based on luminance of incident light.

Abstract: A sensor thin film transistor includes a gate electrode, a gate insulation layer formed on the gate electrode, a semiconductor layer having a portion positioned above the gate electrode and on a side of the gate insulation layer opposite the gate electrode, and a source electrode and drain electrode having spaced apart ends positioned on the semiconductor layer, wherein the sensor thin film transistor is operative such that a signal-to-noise ratio is equal to or greater than about 200 when the gate-off voltage applied to the gate electrode is equal to or less than about 0V.

Abstract: A CMOS image sensor and a fabricating method for a semiconductor device are disclosed. Embodiments provide a CMOS image sensor having an improved structure using a light reflection system, with a fabricating method thereof to simplify the fabrication process and maximize a light receiving area. Embodiments may be applied to a semiconductor device having a lamination structure.

Abstract: Realized is a solid-state imaging device capable of achieving both a finer pixel size and high light receiving efficiency with an excellent image characteristic. A high concentration p-well layer (5) is partially formed in the interior of a semiconductor substrate (1) centering on a region under a STI (6), and a photoelectric conversion layer (9a, 9b) is formed so as to extend to a region under a gate electrode (10a, 10b). Furthermore, a salicide region (12a, 12b) covers only a portion of a surface of the gate electrode (10a, 10b) and is formed at a position closer to a side at which a drain region (13) is provided. Thus, an incident light is allowed to pass through a portion, included in the surface of the gate electrode (10a, 10b), on which the salicide region (12a, 12b) is not formed, and then to be further incident on the photoelectric conversion layer (9a, 9b) extending to the region under the gate electrode (10a, 10b).

Abstract: Provided are an image sensor and a method of manufacturing the same. The image sensor can be vertically arranged image sensor where the photodiode is provided above the circuitry on the substrate. The photodiode can be formed on a lower electrode provided electrically connected to a CMOS circuit on a substrate. The photodiode can have a PIN or PI photodiode structure including an intrinsic layer on the lower electrode and a conductive type layer on the intrinsic layer. A salicide layer can be disposed on the intrinsic layer, and the conductive type conduction layer can be disposed on the salicide layer. The intrinsic layer can be formed to create a light condensing portion, providing a convex-shaped upper surface.

Abstract: A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.

Abstract: An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track.

Abstract: A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.

Abstract: A CMOS image sensor and method for fabricating the same improve image characteristics by eliminating the thickness of a planarization layer.

Abstract: The present invention relates to a method for manufacturing a CMOS image sensor. The method comprises forming a photodiode and a transistor on a semiconductor substrate which is divided into a pixel region and a peripheral region, forming a plurality of oxide films and metal wiring on the semiconductor substrate, depositing a silicon oxynitride (SiON) layer on the oxide film, performing an array etch in the pixel region in order to reduce the optical length of the pixel region, depositing a silicon nitride (SiN) layer over the etched pixel region and silicon oxynitride layer, and forming a micro lens on the silicon nitride layer. Advantageously, the method prevents the generation of circular defects in the peripheral region while maintaining the refractive index in the pixel region.

Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.

Abstract: A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to form a transfer-gate pattern, and then the transfer-gate pattern is used as an etching mask to pattern the gate material layer and form a transfer gate. Ion implantation is then conducted to form a PN diode in the substrate with the transfer-gate pattern and the transfer gate as a mask.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: The present invention provides a display device having an illuminance detection circuit. The illuminance detection circuit includes: a photosensor which changes an optical current in response to illuminance of an external light; a capacitor which discharges a charge when the optical current flows in the photosensor; a comparator which compares a voltage at one end of the capacitor and a comparison reference voltage; a switching circuit which is connected to one end of the capacitor and charges the capacitor in response to a level of an output signal of the comparator; and a selection circuit which applies either a first voltage or a second voltage to the other end of the capacitor in response to the level of the output signal of the comparator.

Abstract: A device is disclosed for sensing radiation, having a gate region and a substrate, wherein one of the gate region and the substrate is configured as an input for radiation. A channel region, connecting a source region and a drain region of the transistor device is provided. The device is configured to produce an electrical signal, which is proportional to the input radiation, at a first location of the channel region.

Abstract: Example embodiments may provide a CMOS image sensor and example methods of forming the same. Example embodiment CMOS image sensors may include a transfer gate insulating pattern between a transfer gate and an active region. A photodiode region and/or a floating doped region may be in the active region at either side of the transfer gate. The transfer gate insulating pattern may include a first part adjacent to the photodiode region and/or a second part adjacent to the floating doped region. The first part may be thicker than the second part.

Abstract: An imaging apparatus capable of suppressing deterioration of image qualities and output properties is provided having one or more output circuits in series and a buffer circuit 6, and processing luminance signals from photodetectors to output image information, the buffer circuit performing impedance conversion on signals outputted from a final output circuit of the one or more output circuits, the final output circuit being a source follower circuit that has an active element and a current source circuit 5 which is inserted between a source terminal of the active element and a reference voltage terminal, wherein the current source circuit and the buffer circuit 6 are external to a solid-state image sensor 1 having the photodetectors, and a main part of the current source circuit 5 and a main part of the buffer circuit 6 are in a single package.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: A MESFET includes a silicon carbide layer, spaced apart source and drain regions in the silicon carbide layer, a channel region positioned within the silicon carbide layer between the source and drain regions and doped with implanted dopants, and a gate contact on the silicon carbide layer. Methods of forming a MESFET include providing a layer of silicon carbide, forming spaced apart source and drain regions in the silicon carbide layer, implanting impurity atoms to form a channel region between the source and drain regions, annealing the implanted impurity atoms, and forming a gate contact on the silicon carbide layer.

Abstract: In an optical sensor device employing an amorphous silicon photodiode, an external amplifier IC and the like are required due to low current capacity of the sensor element in order to improve the load driving capacity. It leads to increase in cost and mounting space of the optical sensor device. In addition, noise may easily superimpose since the photodiode and the amplifier IC are connected to each other over a printed circuit board. According to the invention, an amorphous silicon photodiode and an amplifier configured by a thin film transistor are formed integrally over a substrate so that the load driving capacity is improved while reducing cost and mounting space. Superimposing noise can be also reduced.

Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Abstract: A semiconductor device includes a conducting channel (130) formed beneath a substrate surface with a pre-determined photo-conductivity spectral response. The channel is formed between two pn-junctions (126, 128) defining first and third photo-electric depletion regions at respective depths relative to the surface corresponding to penetration depths of light of different wavelengths. The first region (106) which has the light absorbing surface (104) above the first pn-junction (126) is specific to a first colour. The channel region (130) between the two pn-junctions (126, 128) is photo-conductive to a second colour. The third region below the second pn-junction (128) is sensitive to a third colour. Electrical contacts (118, 120, 122, 124) are disposed on the source (112), the top gate (106), the drain (114) and the bottom gate (116) for receiving the electrical currents induced by the presence of the absorbed wavelengths.