Abstract: One embodiment relates to a method of manufacturing a magnetic sensor. In the method, an engagement surface is provided. A magnet body is formed over the engagement surface by gradually building thickness of a magnetic material. The magnet body has a magnetic flux guiding surface that substantially corresponds to the engagement surface. Other apparatuses and methods are also set forth.

Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.

Abstract: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.

Abstract: A magnetic element includes a channel layer, a first magnetic electrode which is in contact with the channel layer, a second magnetic electrode which is in contact with the channel layer and is insulated from the first magnetic electrode, a first intermediate layer which is provided adjacent to the first magnetic electrode and has a first insulating layer, a first magnetic layer which is provided in contact with a surface of the first intermediate layer on an opposite side to a surface contacting the first magnetic electrode to transfer magnetization to the first magnetic electrode, a first electrode which is connected to the first magnetic electrode, and a second electrode which is connected to the second magnetic electrode, at least one of the first electrode and the second electrode outputting a first signal which changes depending on a magnetic arrangement of the first magnetic electrode and the second magnetic electrode.

Abstract: Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value.

Abstract: When a gate voltage VGS is applied, the Schottky barrier width due to the metallic spin band in the ferromagnetic source is decreased, and up-spin electrons from the metallic spin band are tunnel-injected into the channel region. However, down-spin electrons from the nonmagnetic contact (3b) are not injected because of the energy barrier due to semiconductive spin band of the ferromagnetic source (3a). That is, only up-spin electrons are injected into the channel layer from the ferromagnetic source (3a). If the ferromagnetic source (3a) and the ferromagnetic drain (5a) are parallel magnetized, up-spin electrons are conducted through the metallic spin band of the ferromagnetic drain to become the drain current. Contrarily, if the ferromagnetic source (3a) and the ferromagnetic drain (5a) are antiparallel magnetized, up-spin electrons cannon be conducted through the ferromagnetic drain (5a) because of the energy barrier Ec due to the semiconductive spin band in the ferromagnetic drain (5a).

Abstract: A method of manufacturing a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, depositing a conductive terminal within the trench, and depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a configurable magnetic orientation. The fixed magnetic layer is coupled to the conductive terminal along an interface that extends substantially normal to a surface of the substrate. The free magnetic layer that is adjacent to the conductive terminal carries a magnetic domain adapted to store a digital value.

Abstract: The present invention provides a novel element capable of simply controlling an in-plane rotational motion of a core (a rising spot of a magnetization) generated in the center of a ferromagnetic dot made by forming a ferromagnetic material into a nanosized disk shape. In addition, the present invention is achieved to provide a binary information memory element using a core, including a ferromagnetic dot, made of a disk-shaped ferromagnetic material, with a magnetic structure of a magnetic vortex structure, and a current supplier for supplying an alternating current with a predetermined alternating current in the radial direction of the ferromagnetic dot. In the case where the frequency of the current resonates with the intrinsic frequency of the ferromagnetic dot, it is possible to rotate the core in the plane of the dot. Since the core leaks a magnetic field, a microscopic actuator such as a motor can be obtained by using this element.

Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.

Abstract: Exchange-coupled magnetic multilayer structures for use with toggle MRAM devices and the like include a tunnel barrier layer (108) and a synthetic antiferromagnet (SAF) structure (300) formed on the tunnel barrier layer (108), wherein the SAF (300) includes a plurality (e.g., four or more) of ferromagnetic layers (302, 306, 310, 314) antiferromagnetically or ferromagnetically coupled by a plurality of respective coupling layers (304, 308, 312). The microcrystalline texture of one or more of the ferromagnetic layers is reduced to substantially zero as measured from X-Ray Diffraction by exposure of various layers to oxygen, by forming a detexturing layer, by adding oxygen during the ferromagnetic or coupling layer fabrication, and/or by using amorphous materials.

Abstract: New kinds of nano-scale computational architectures using spin waves as a physical mechanism for device interconnection are described. A method for operating a logic device having a spin wave bus includes the step of receiving an input signal representing information. A spin wave is excited with the information coded in an aspect of the spin wave in response to receiving the input signal. The spin wave is propagated through a spin wave bus having an associated polarization. The information associated with the spin wave is determined in response to propagating the spin wave through the spin wave bus.

Abstract: Provided may be a semiconductor device using magnetic domain wall movement. The semiconductor device may include a magnetic track having a plurality of magnetic domains and a thermal conductive insulating layer configured to contact the magnetic track. The thermal conductive insulating layer may prevent or reduce the magnetic track from being heated due to a current supplied to the magnetic track.

Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.

Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.

Abstract: A micro-generator includes an integrated circuit (IC) wafer. A micro-electro mechanical system (MEMS) wafer, with a movable micromechanical element, is bonded to the IC wafer. A plurality of first metal coils associated with a plurality of trenches is arranged in one of the IC wafer and the MEMS wafer. A plurality of micro-magnets is provided in the other of the IC wafer and the MEMS wafer. Each micro-magnet is associated with a respective trench and is formed from a magnet layer deposited, plated or bonded to the MEMS wafer or IC wafer. Movement of the micro-mechanical element generates a voltage in the first metal coils.

Abstract: Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back side grinding process but prior to removal of back side grinding tape. Thus, debris generated from the scribing process is prevented from being deposited on a top surface of the wafer. To determine the location of dicing lanes or streets relative to the back side of the wafer, the top side of the wafer is illuminated with a light configured to pass through the grinding tape and the wafer. The light is detected from the back side of the wafer, and the streets are mapped relative to the back side. The back side of the wafer is then cut with a saw or laser.

Abstract: A magnetic body composed of non-magnetic material, includes a plurality of localized electron regions in each of which at least one electron is confined to form a localized spin, a barrier potential region having a higher energy than a Fermi energy of an electron in the localized electron region and permitting an electron to be confined in the respective localized electron regions, and a conductive electron region including a conductive electron system having a lower energy than an energy of the barrier potential region, wherein the respective localized electron regions are disposed separate from one another via the barrier potential region and the conductive electron region.

Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.

Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.

Abstract: Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

Abstract: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the electrode portion on the surface of the semiconductor chip. The electrode portion is placed in a position which does not overlap with the sensor element in the thickness direction of the semiconductor chip.

Abstract: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.

Abstract: A semiconductor device including: a substrate comprising silicon; a channel region formed on the substrate; a spin injector formed on the substrate at a first side of the channel region and configured to diffuse a spin-polarized current into the channel region; a spin detector formed on the substrate at a second side of the channel region and configured to receive the spin polarized current from the channel region; and a gate formed on the substrate in an area of the channel region.

Abstract: One embodiment of the present invention provides a switching device that can vary a spin-polarized current based on an input signal. The switching device comprises a first conducting region, a second conducting region, and a half-metal region interposed between the first conducting region and the second conducting region. The half-metal region comprises a material which, at the intrinsic Fermi level, has substantially zero available electronic states in a minority spin channel. Changing the voltage of the half-metal region with respect to the first conducting region moves its Fermi level with respect to the electron energy bands of the first conducting region, which changes the number of available electronic states in the majority spin channel, and in doing so, changes the majority-spin polarized current passing through the switching device.

Abstract: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the electrode portion on the surface of the semiconductor chip. The electrode portion is placed in a position which does not overlap with the sensor element in the thickness direction of the semiconductor chip.

Abstract: A semiconductor device, comprising a semiconductor chip; a pad electrode; an electrode portion; a wiring portion. An insulating portion is formed from electrically insulating material, covering the surface of the semiconductor chip and sealing the sensor element, wiring portion and electrode portion, in a state which exposes at least the electrode portion on the surface of the semiconductor chip. The electrode portion is placed in a position which does not overlap with the sensor element in the thickness direction of the semiconductor chip.

Abstract: A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate. The semiconductor region is a diffusion layer including a conductive impurity doped and diffused therein. The semiconductor region is made of diffusion layer so that the device has high design degree of freedom.

Abstract: A MgO tunnel barrier is sandwiched between semiconductor material on one side and a ferri- and/or ferromagnetic material on the other side to form a spintronic element. The semiconductor material may include GaAs, for example. The spintronic element may be used as a spin injection device by injecting charge carriers from the magnetic material into the MgO tunnel barrier and then into the semiconductor. Similarly, the spintronic element may be used as a detector or analyzer of spin-polarized charge carriers by flowing charge carriers from the surface of the semiconducting layer through the MgO tunnel barrier and into the (ferri- or ferro-) magnetic material, which then acts as a detector. The MgO tunnel barrier is preferably formed by forming a Mg layer on an underlayer (e.g., a ferromagnetic layer), and then directing additional Mg, in the presence of oxygen, towards the underlayer.

Abstract: A magnetic random access memory includes a substrate; a first ferromagnetic layer; a magnetic tunnel junction (MTJ) device provided on a same side of the substrate as the first ferromagnetic layer; and a wiring layer provided between the first ferromagnetic layer and the MTJ device. The MTJ device includes a second ferromagnetic layer opposing to the wiring layer. A first perpendicular projection of the first ferromagnetic layer on the substrate and a second perpendicular projection of the second ferromagnetic layer on the substrate are different in area, and one of the first and second perpendicular projections contains the other.

Abstract: A method and system for providing a magnetic element is disclosed. The magnetic element include providing a pinned layer, a spacer layer, and a free layer. The method and system also include providing a heat assisted switching layer and a spin scattering layer between the free layer and the heat assisted switching layer. The spin scattering layer is configured to more strongly scatter majority electrons than minority electrons. The heat assisted switching layer is for improving a thermal stability of the free layer when the free layer is not being switched. Moreover, the magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.

Abstract: The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at least a part of a magnetic yoke, as compared with the case of formation by a dry film forming method, sufficient thickness and higher dimensional precision can be obtained. Consequently, a more stabilized return magnetic field can be generated and high reliability can be assured. Neighboring memory cells can be disposed at narrower intervals, so that the invention is suitable for realizing higher integration and higher packing density.