Assembling Bases Patents (Class 29/830)
-
Patent number: 11973045Abstract: A semiconductor structure includes: a first substrate, with a first opening being provided on a surface of first substrate; and a first bonding structure positioned in the first opening. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than that of the first metal layer. The first metal layer includes a first surface in contact with a bottom surface of the first opening and a second surface opposite to the first surface, the second surface is provided with a first groove, an area, not occupied by the first metal layer and the first groove, of the first opening constitutes a second groove, the second metal layer is formed in the first groove and the second groove, and a surface, exposed from the second groove, of the second metal layer constitutes a bonding surface of the first bonding structure.Type: GrantFiled: February 11, 2022Date of Patent: April 30, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ling-Yi Chuang
-
Patent number: 11967540Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.Type: GrantFiled: December 1, 2021Date of Patent: April 23, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Seungwon Im, Oseob Jeon, Byoungok Lee, Yoonsoo Lee, Joonseo Son, Dukyong Lee, Changyoung Park
-
Patent number: 11961742Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: August 23, 2021Date of Patent: April 16, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
-
Patent number: 11953521Abstract: Provided is a probe card, comprising a guide plate and a shielding structure of single-layer or multi-layer. The guide plate comprises an upper surface, a lower surface, and at least one guide hole passing through the upper surface and the lower surface, and the guide hole is provided with an inner wall surface. At least one layer of the shielding structure is made of an electromagnetic absorption material or an electromagnetic reflection material, and the shielding structure is not connected to a ground. Each layer of the shielding structure is formed on the inner wall surface of the guide hole by means of atomic layer deposition or atomic layer etching, and a thickness of each layer is less than 1000 nm.Type: GrantFiled: August 10, 2022Date of Patent: April 9, 2024Assignee: BAO HONG SEMI TECHNOLOGY CO., LTD.Inventors: Chao-Cheng Ting, Li-Hong Lu, Huai-Yi Wang, Lung-Chuan Tsai
-
Patent number: 11946847Abstract: An extracellular potential measurement device includes multiple insulating films each of which is made from an electric insulating material, the insulating films being stacked and bonded to each other; and multiple electrode wires each of which is made from an electroconductive material, the electrode wires being arranged in multiple heights. Each of the electrode wires is interposed between an upper insulating film and a lower insulating film. Each of the insulating films, except for a lowermost insulating film, has an opening penetrating the insulating film. The opening in a lower insulating film has a size that is less than that of the opening in an upper insulating film, the openings in the insulating films being overlapped to form a recess having a size reducing downward, the recess being adapted to store a collection of cells. Each of the electrode wires has an end that is located near an opening in an insulating film that is immediately below the electrode wire, the ends being exposed in the recess.Type: GrantFiled: October 1, 2020Date of Patent: April 2, 2024Assignees: NOK CORPORATION, THE UNIVERSITY OF TOKYOInventors: Takayuki Komori, Keiichi Miyajima, SooHyeon Kim, Teruo Fujii, Shinji Okawa
-
Patent number: 11940346Abstract: A micromechanical pressure sensor device including a semiconductor base substrate of a first doping type on which an intermediate layer of the first doping type is situated, a cavity sealed by a sealing layer of a second doping type and including a reference pressure, a first grating of the second doping type, suspended inside the cavity on a buried connection region of the second doping type, the buried connection region laterally extending away from the cavity into the semiconductor base material, a second grating of the second doping type, situated on a side of the diaphragm region pointing to the cavity and suspended on the diaphragm region, the first grating and the second grating being electrically insulated from each other and forming a capacitance, a first connection electrically connected to the first grating via the buried connection region, and a second connection electrically connected to the second grating.Type: GrantFiled: December 13, 2019Date of Patent: March 26, 2024Assignee: ROBERT BOSCH GMBHInventors: Johannes Meckbach, Thomas Friedrich
-
Patent number: 11917769Abstract: The present application relates to the technical field of circuit board fabricating, and provides a method for fabricating an asymmetric board, the method includes fabricating a master board, fabricating a second sub-board, thermal compression bonding the master board and the second sub-board, and milling an asymmetric board; further includes at least one of the following three steps: laying copper on the connection areas of the master board except for the second copper layer of an outermost layer to obtain laying copper area, removing copper on the connection areas of the third copper layer, and after the step of milling the asymmetric board, on each of the sub-boards, performing depth control milling at the connection areas from a side of the second sub-board on each sub-board to obtain a depth control groove.Type: GrantFiled: March 4, 2021Date of Patent: February 27, 2024Assignee: SHENZHEN KINWONG ELECTRONIC CO., LTD.Inventors: Jun Wang, Xiaoqing Chen, Qian Chen
-
Patent number: 11915986Abstract: A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.Type: GrantFiled: February 28, 2022Date of Patent: February 27, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ramlah Binte Abdul Razak, Hector Torres
-
Patent number: 11907452Abstract: A display device includes a window member, a display panel, a first adhesive member, and a reinforcing member. The display panel is disposed below the window member. The first adhesive member is disposed between the window member and the display panel. The first adhesive member overlaps the display panel. The reinforcing member is disposed below the display panel such that the display panel is disposed between the window member and the reinforcing member. On a plane of the window member, a first minimum distance from an outermost portion of the window member to an outermost portion of the display panel is equal to a second minimum distance from the outermost portion of the window member to an outermost portion of the first adhesive member.Type: GrantFiled: October 18, 2021Date of Patent: February 20, 2024Assignee: Samsung Display Co., Ltd.Inventors: Ah-Ram Lee, Seongsik Ahn
-
Patent number: 11908784Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.Type: GrantFiled: September 23, 2020Date of Patent: February 20, 2024Assignee: NXP USA, Inc.Inventors: Akhilesh Kumar Singh, Andrew Jefferson Mawer, Nishant Lakhera, Chee Seng Foong, Nihaar N. Mahatme
-
Patent number: 11901298Abstract: A semiconductor device has a semiconductor chip having a plurality of pads and wires electrically connected to the plurality of pads, respectively. The plurality of pads includes a plurality of first pads which is electrically connected to a circuit included in the semiconductor chip and to which first wires are bonded and a second pad which is an electrode pad for wire connection test and to which a second wire is bonded.Type: GrantFiled: November 5, 2021Date of Patent: February 13, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Kenji Ikura
-
Patent number: 11881643Abstract: Provided is an electrical connection member including a conductive member made of a rubber-like elastic material, through which a terminal used for supplying power is mounted to a mounted member such as a glass plate, and electrically connected with a small electric resistance to contact member provided in the mounted member, resulting in less reduction of rubber-like elasticity of the conductive member due to a temperature increase of the electrical connection member, even if large current flows. With respect to the conductive member 11 made of the rubber-like elastic material provided in the electrical connection member 10, a compression set measured after the following treatment is 50% or less, the treatment being comprise applying a load between an upper surface and a lower surface of the conductive member and conducting 25% compressive deformation at 105° C. for 22 hours; and electric resistance between the upper surface and the lower surface is 0.1? or less during application of the load.Type: GrantFiled: March 6, 2020Date of Patent: January 23, 2024Assignee: SEKISUI POLYMATECH CO., LTD.Inventors: Hideaki Konno, Yasuyoshi Watanabe, Tsubasa Kamiya
-
Patent number: 11877404Abstract: Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1 ?m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500 ?m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin therebetween or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.Type: GrantFiled: March 22, 2021Date of Patent: January 16, 2024Assignee: Averatek CorporationInventor: Shinichi Iketani
-
Patent number: 11876317Abstract: The present invention relates to an electrical connection device and an electronic device comprising same, wherein a receptacle includes a plurality of conductive terminals that are arranged to press a connector in different directions and induces stable contact when the connector is connected to the receptacle.Type: GrantFiled: October 18, 2019Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Inha Lee, Seoungho Jung, Hanseok Mun, Jaeryong Han
-
Patent number: 11856713Abstract: A multilayer resin substrate includes a stacked body including resin layers stacked on each other, a first planar conductor on a resin layer, and an interlayer connection conductor on a resin layer. The interlayer connection conductor includes a first interlayer connection conductor connected to an external conductor, and a second interlayer connection conductor bonded to the first interlayer connection conductor and a planar conductor. The first and second interlayer connection conductors are made of different materials. The second interlayer connection conductor includes a constricted portion including a smaller planar cross-sectional area than a different portion, between a bonding portion to which the first interlayer connection conductor is bonded and a bonding portion to which the planar conductor is bonded.Type: GrantFiled: September 10, 2021Date of Patent: December 26, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masanori Okamoto, Takeshi Osuga
-
Patent number: 11821938Abstract: A rigid-flex printed circuit board (PCB) includes at least one rigid PCB including at least one electrical component, a flex circuit, and a built-in diagnostic circuit. The flex circuit includes at least one end connected to the at least one rigid PCD. The flex circuit includes at least one signal trace configured to deliver an electrical signal to the at least one electrical component. The built-in diagnostic circuit is configured to detect a fault in the rigid-flex PCB.Type: GrantFiled: December 2, 2021Date of Patent: November 21, 2023Assignee: HAMILTON SUNDSTRAND CORPORATIONInventor: Gomathi Ganesh Narayanan
-
Patent number: 11825725Abstract: An electronic apparatus includes a display panel including a base substrate including an active area and a peripheral area adjacent to the active area, pixels on the active area, pads on the peripheral area and arranged in a first direction, signal lines connecting the pixels to the pads, and a vernier mark on the peripheral area and spaced apart from the pads and the signal lines, a circuit board on the display panel and including a base film, and leads on the base film and overlapping with the pads in a plan view, and a conductive adhesive member extending in the first direction and between the display panel and the circuit board to connect the pads to the leads. The conductive adhesive member overlaps with the vernier mark when viewed in a second direction intersecting the first direction.Type: GrantFiled: July 26, 2022Date of Patent: November 21, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jun-yong An, Yun-kyeong In, Junwon Choi, Wonmi Hwang
-
Patent number: 11798887Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.Type: GrantFiled: October 1, 2021Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
-
Patent number: 11784140Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.Type: GrantFiled: July 27, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiun Yi Wu, Chen-Hua Yu
-
Patent number: 11778738Abstract: A printed circuit board assembly includes a main printed circuit board including a first main signal line and a first dielectric having a first permittivity; a sub printed circuit board including a first sub signal line and a second dielectric having a second permittivity smaller than the first permittivity; and a first connection block configured to connect the first main signal line of the main printed circuit board and the first sub signal line of the sub printed circuit board.Type: GrantFiled: August 20, 2019Date of Patent: October 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hoon Hwangbo
-
Patent number: 11764198Abstract: A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.Type: GrantFiled: March 2, 2017Date of Patent: September 19, 2023Assignee: EV Group E. Thallner GmbHInventor: Markus Wimplinger
-
Patent number: 11764344Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.Type: GrantFiled: March 22, 2021Date of Patent: September 19, 2023Assignee: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang
-
Patent number: 11749514Abstract: The invention relates to methods for drawing-off liquid from individual droplets which are in a predefined arrangement on a flat substrate and have sedimented material enclosed in them. A mask of an absorbent material comprising a pattern of indentations or holes which corresponds at least partially to the regular arrangement of the individual droplets, or a stiff, rigid plate of an absorbent material is positioned above the flat substrate in such a way that the droplets come into contact with the absorbent material peripherally so that liquid is drawn off there-into. The invention also relates to a mask of an absorbent material with a substantially rectangular shape which has a predefined pattern of indentations or holes for the purpose of separating liquid and sedimented material enclosed therein.Type: GrantFiled: March 31, 2021Date of Patent: September 5, 2023Inventors: Martin Schürenberg, Alexander Vossgröne
-
Patent number: 11721882Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: GrantFiled: October 20, 2020Date of Patent: August 8, 2023Assignee: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
-
Patent number: 11721793Abstract: A display device includes: a display module; a driving chip assembly electrically connected to the display module and including a driving chip and a heat dissipator at least partially surrounding the driving chip; and a main circuit board electrically connected to the driving chip assembly and contacting the heat dissipator.Type: GrantFiled: November 11, 2020Date of Patent: August 8, 2023Assignee: Samsung Display Co., Ltd.Inventor: Yeongsang Suh
-
Patent number: 11706873Abstract: A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.Type: GrantFiled: October 5, 2021Date of Patent: July 18, 2023Assignee: IBIDEN CO., LTD.Inventor: Shigeto Iyoda
-
Patent number: 11682526Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer, first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween in the ceramic body, and first and second external electrodes disposed on external surfaces of the ceramic body and electrically connected to the first and second electrodes. At least one of the first and second external electrodes includes a first electrode layer including a first glass and a second electrode layer disposed on the first electrode layer and including a second glass. The first glass contains a larger amount of barium-zinc (Ba—Zn) than the second glass, and the second glass contains a larger amount of silicon (Si) than the first glass.Type: GrantFiled: July 8, 2021Date of Patent: June 20, 2023Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hye Min Bang, Bum Su Kim, Hyun Hee Gu, Hee Sang Kang
-
Patent number: 11670613Abstract: An arrangement, a method of manufacturing component carriers and a component carrier are provided. The arrangement includes a central carrier structure having a front side and a back side, a first layer stack having a first surface structure made of another material than the interior of the first layer stack and covered by a first release layer which is attached to the front side, and a second layer stack covered by a second release layer which is attached to the back side.Type: GrantFiled: December 14, 2020Date of Patent: June 6, 2023Assignee: AT&S (China) Co. Ltd.Inventors: Mikael Tuominen, Nick Xin, Seok Kim Tay
-
Patent number: 11650570Abstract: A card manufacturing system includes a locating device and a separation device. A laminate sheet comprising a plurality of cards is received by the locating device and is imaged using first and second imaging modalities. The first imaging modality identifies a location of each of the plurality of information carrying cards within the laminate sheet and the second imaging modality images at least one graphic formed on a surface of the laminate sheet. A position of the at least one graphic with respect to at least one information carrying card is determined and the plurality of cards are removed from the laminate sheet using information corresponding to the location of each of the plurality of information carrying cards when the position of the at least one graphic with respect to the information carrying cards is within a predetermined range.Type: GrantFiled: January 15, 2019Date of Patent: May 16, 2023Assignee: Idemia America Corp.Inventor: Mark A. Cox
-
Patent number: 11621491Abstract: A chip antenna includes a first substrate, a second substrate overlapping the first substrate, a first patch, provided on a first surface of the first substrate, operating as a feed patch, a second patch, provided on the second substrate, operating as a radiation patch, at least one feed via penetrating through the first substrate in a thickness direction and configured to provide a feed signal to the first patch, and a ground pad provided on the other surface of the first substrate. The first substrate comprises a ceramic sintered material. The ceramic sintered material comprises an Mg2SiO4 phase, an MgAl2O4 phase, and a CaTiO3 phase, and a content of the CaTiO3 phase in the ceramic sintered material ranges from 5.1 mol % to 15.1 mol %.Type: GrantFiled: September 1, 2021Date of Patent: April 4, 2023Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jae Yeong Kim, Chin Mo Kim, Ji Hyung Jung, Sung Nam Cho, Sung Yong An
-
Patent number: 11622446Abstract: A wiring substrate includes a resin insulating layer, a conductor pad formed on the resin insulating layer, a coating insulating layer formed on the resin insulating layer such that the coating insulating layer is covering the conductor pad, and a metal post connected to the conductor pad and protruding from the coating insulating layer such that a gap is formed between the metal post and the conductor pad at a peripheral edge of the metal post. The coating insulating layer is formed such that the coating insulating layer has an interposed portion formed in the gap between the metal post and the conductor pad at the peripheral edge of the metal post.Type: GrantFiled: June 28, 2021Date of Patent: April 4, 2023Assignee: IBIDEN CO., LTD.Inventors: Isao Ohno, Tomoya Daizo, Yoji Sawada, Kazuhiko Kuranobu
-
Patent number: 11610714Abstract: A slow wave inductive structure includes a first substrate. The slow wave inductive structure further includes a first conductive winding over the first substrate. The slow wave inductive structure further includes a second substrate over the first substrate, wherein a distance between the first conductive winding and the second substrate ranges from about 1 micron (?m) to about 2 ?m, and the second substrate comprises polysilicon or doped silicon. The slow wave inductive structure further includes a second conductive winding on an opposite side of the second substrate from the first conductive winding.Type: GrantFiled: November 20, 2019Date of Patent: March 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo
-
Patent number: 11605766Abstract: A light-emitting module includes: a light-transmitting lightguide plate; light sources disposed on the lightguide plate, each light source including a light-emitting element and a cover member including a first resin and provided beside a lateral surface of the light-emitting element, with first and second electrodes exposed through the cover member; a light-reflecting member provided on the lightguide plate and provided around the light sources, with the cover members of exposed through the light-reflecting member, wherein the light-reflecting member includes a second resin having a higher hardness than the first resin; a support layer covering the light-reflecting member and the cover members, with the first electrodes and the second electrodes exposed through the support layer, wherein the support layer includes a third resin having a higher hardness than the first resin; and a wiring layer provided on the support layer and connected to the first electrodes and the second electrodes.Type: GrantFiled: December 28, 2020Date of Patent: March 14, 2023Assignee: NICHIA CORPORATIONInventor: Takayoshi Wakaki
-
Patent number: 11554585Abstract: A liquid ejecting head includes wiring members including a first-wiring member having a first-output terminal portion extending in a first-direction and a first-input terminal portion extending in the first-direction, and a second-wiring member having a second-output terminal portion extending in the first-direction and a second-input terminal portion extending in the first-direction; and a first-wiring substrate coupled to the first and second input terminal portions, in which a center of the first-output terminal portion is located in the first-direction with respect to a center of the second-output terminal portion in plan view, a center of the first-input terminal portion is disposed in a second-direction opposite to the first-direction with respect to the center of the first-output terminal portion in the plan view, and a center of the second-input terminal portion is disposed in the first-direction with respect to the center of the second-output terminal portion in the plan view.Type: GrantFiled: June 1, 2021Date of Patent: January 17, 2023Assignee: Seiko Epson CorporationInventor: Hiroaki Okui
-
Patent number: 11545412Abstract: A package structure including a circuit board and a heat generating element is provided. The circuit board includes a plurality of circuit layers and a composite material layer. A thermal conductivity of the composite material layer is between 450 W/mK and 700 W/mK. The heat generating element is disposed on the circuit board and electrically connected to the circuit layers. Heat generated by the heat generating element is transmitted to an external environment through the composite material layer.Type: GrantFiled: November 19, 2020Date of Patent: January 3, 2023Assignee: Unimicron Technology Corp.Inventors: Pei-Wei Wang, Ching Sheng Chen, Ra-Min Tain, Ming-Hao Wu, Hsuan-Wei Chen
-
Patent number: 11540388Abstract: Disclosed are a flexible circuit board component and a display device. The flexible circuit board component includes a flexible circuit board and a foam structure. The flexible circuit board includes a first area and a second area which are arranged in a first direction and connected to each other. The foam structure is located on a side of the first area in the flexible circuit board, and includes a first foam and a second foam, and in the first direction, the second foam is located between the first foam and the second area. After the flexible circuit board component is affixed to a non-light-emitting display side of a display panel, in a direction perpendicular to an interface of the foam structure and the flexible circuit board, a height of the second foam on a side adjacent to the second area is less than a height of the first foam.Type: GrantFiled: April 7, 2021Date of Patent: December 27, 2022Assignees: WUHAN TIANMA MICROELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCHInventor: Wei Shi
-
Patent number: 11532906Abstract: A power delivery system for a hardware processor includes a motherboard (MB), a voltage regulator (VR), an elastomer computer socket, and a plurality of power delivery paths within the socket. The socket connects the MB to the processor and comprises a first set of power pins that is connected to the processor by surface mount elements, and a second set of power pins that is not connected to the processor by surface mount elements. The plurality of electrical power delivery paths deliver VR power from the second set of C power pins to the first set of power pins for power delivery to the processor. The alignment frame aligns the processor, the plurality of power pins, and the MB. The plurality of power paths alone may meet the power demands of the processor. If not, a power plane from the MB provides additional power.Type: GrantFiled: June 29, 2018Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Yi Huang, Fernando Gonzalez Lenero, Liwei Zhao
-
Patent number: 11523493Abstract: An electronic control unit includes: a wiring substrate having a first surface on which a conductor wire is formed; a first electronic component that is implemented on the first surface of the wiring substrate, and has a large heat generation amount; a second electronic component that is implemented on the first surface of the wiring substrate, and has a heat generation amount smaller than the first electronic component; and a resin that covers the first electronic component, the second electronic component, and the first surface of the wiring substrate, and a second surface of the wiring substrate that is opposite to the first surface. A distance between an outer surface of the resin immediately below the first electronic component, and the second surface of the wiring substrate is longer than a distance between an outer surface of the resin immediately above the second electronic component, and the first surface of the wiring substrate.Type: GrantFiled: June 27, 2019Date of Patent: December 6, 2022Assignee: Hitachi Astemo, Ltd.Inventors: Miki Hiraoka, Ryosuke Ishida, Yoshio Kawai
-
Patent number: 11495525Abstract: A module has electronic components mounted to a Printed Circuit Board (PCB) with multiple patterned conductive layers connecting to conductive slot metal around a conductive slot. A groove is cut through a top molding encapsulant above and into the conductive slot but does not cut through a bottom molding encapsulant. A terminal pin is inserted into the groove and pushed down into the conductive slot. When heated, embedded solder previously applied to the conductive slot metal flows between the end of the terminal pin and the conductive slot metal to form a solder bond. An end of the PCB past the conductive slot has no metal traces, preventing shorts. Epoxy can be placed into the groove around the terminal pin or a hole formed in the terminal pin to increase strength of the anchored terminal pin. The molding around the groove protects terminal pins from shorting from the side.Type: GrantFiled: March 3, 2021Date of Patent: November 8, 2022Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventors: Lourdito M. Olleres, Shi Wo Chow
-
Patent number: 11482437Abstract: A method for manufacturing a printed wiring board which includes: Step (A) of laminating an adhesive sheet including a support and a resin composition layer bonded to the support to an inner layer board so that the resin composition layer is bonded to the inner layer board; Step (B) of thermally curing the resin composition layer to form an insulating layer; and Step (C) of removing the support, in this order, in which the support satisfies a condition (MD1): a maximum expansion coefficient EMD in an MD direction at 120° C. or more is less than 0.2% and a condition (TD1): a maximum expansion coefficient ETD in a TD direction at 120° C. or more is less than 0.2% below, when being heated under predetermined heating conditions, does not lower the yield even when the insulating layer is formed by thermally curing the resin composition layer with a support attached to the resin composition layer.Type: GrantFiled: March 19, 2020Date of Patent: October 25, 2022Assignee: Ajinomoto Co., Inc.Inventors: Masanori Ohkoshi, Hirohisa Narahashi, Eiichi Hayashi
-
Patent number: 11457532Abstract: A method for manufacturing a circuit board comprises steps of providing a single-sided board comprising a first insulating base, a copper layer, and at least one first conductive structure; providing a laminated board comprising a metal layer, a third insulating base, a metal shielding layer, and a second insulating base; forming a wiring layer by the metal layer comprising at least one signal wire and at least one connecting pad; defining at least one second through hole each passing through the second insulating base, the metal shielding layer, and the third insulating base; forming a second conductive structure in each second through hole; providing a double-sided board comprising a wiring layer, a fourth insulating base, a first copper foil; and at least one third conductive structure; pressing the single-sided board, at least one middle structure, and the double-sided board in that sequence to form the circuit board.Type: GrantFiled: December 19, 2018Date of Patent: September 27, 2022Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.Inventors: Fu-Yun Shen, Ming-Jaan Ho, Hsiao-Ting Hsu, Lin-Jie Gao
-
Patent number: 11445596Abstract: A circuit board includes an open substrate and a heat dissipation block. The open substrate includes a substrate body, an opening and at least one first fixing portion and at least one second fixing portion. The substrate body has a top surface and a bottom surface. The opening is in the substrate body and has a first sidewall and a second sidewall opposite to the first sidewall. The first fixing portion and the second fixing portion extends from the substrate body toward the opening, in which the first fixing portion and the second fixing portion are respectively protruded from the first sidewall and the second sidewall. The heat dissipation block is directly clamped between the first fixing portion and the second fixing portion.Type: GrantFiled: January 20, 2021Date of Patent: September 13, 2022Assignee: Unimicron Technology Corp.Inventors: Chin-Sheng Wang, Pei-Chang Huang
-
Patent number: 11439023Abstract: A system for providing selective adhesion printed circuit board (PCB) production comprises a conveyor mechanism, a curing system, and a computer. The conveyor mechanism is configured to convey a series of selective adhesion blanks, wherein each selective adhesion blank is utilized to produce a PCB and includes a flexible film, a substrate, a conductive layer, and a curable adhesive. The conductive layer is formed from electrically conductive material and adhered to the substrate. The curable adhesive is positioned between the flexible film and the conductive layer and is configured to selectively bond with the conductive layer when the curable adhesive is cured. The curing system is configured to cure the curable adhesive. The computer includes a processing element configured or programmed to: receive a plurality of PCB designs, and direct the curing system to cure the curable adhesive of a plurality of selective adhesion blanks for each PCB design.Type: GrantFiled: March 12, 2020Date of Patent: September 6, 2022Assignee: Honeywell Federal Manufacturing & Technologies, LLCInventors: Jonathan Douglas Hatch, Stephen McGarry Hatch
-
Patent number: 11424563Abstract: A method for manufacturing a board-to-board connecting structure, including providing a first circuit board, including a first dielectric layer, a second dielectric layer stacked on the first dielectric layer, and a first wiring layer sandwiched between the first dielectric layer and the second dielectric layer. A second circuit board is provided, including a third dielectric layer, a fourth dielectric layers stacked on the third dielectric layer, and a second wiring layer sandwiched between the third dielectric layer and the fourth dielectric layer. The first step and the fourth dielectric layer are bonded through a first adhesive layer. The third step and the dielectric layer are bonded through a second adhesive layer. The second step and the fourth step are bonded through the conductive layer.Type: GrantFiled: November 26, 2020Date of Patent: August 23, 2022Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO.,LTD, GARUDA TECHNOLOGY CO., LTDInventors: Xiao-Feng Zheng, Xiao-Peng Rong
-
Patent number: 11416690Abstract: A memory card reader body includes proposed, on an internal face, a receiving recess to receive a memory card connector. The receiving recess has electrically conductive tracks forming a protective mesh for the memory card connector. The conductive tracks are such that they also extend on an external face of the memory card reader body through vias passing through the internal and external faces.Type: GrantFiled: November 3, 2016Date of Patent: August 16, 2022Assignee: BANKS AND ACQUIRERS INTERNATIONAL HOLDINGInventors: Stephane Pavageau, Jean-Jacques Delorme, Johann Jadeau
-
Patent number: 11417255Abstract: The present invention discloses a driving circuit for a display panel and a display device. The driving circuit includes a driving circuit board configured to carry a driving circuit, and first pads located on the driving circuit. The first pads are connected through a detachable connector.Type: GrantFiled: November 21, 2018Date of Patent: August 16, 2022Assignee: HKC CORPORATION LIMITEDInventor: Jianfeng Shan
-
Patent number: 11416729Abstract: The present invention relates to a metal card manufacturing method including the steps of: preparing a metal sheet having a given size capable of accommodating a plurality of individual cards; forming holes on at least one or more edges of stacked sheets formed by stacking a plurality of sheets inclusive of adhesive sheets and an inlay sheet on which antenna coils are printed, the plurality of sheets having the same size capable of accommodating the plurality of individual cards as each other; fitting the holes formed on the stacked sheets to pins located on a loading plate; placing the metal sheet on top of the stacked sheets; forming a metal card sheet through lamination among the metal sheet and the stacked sheets; and cutting the metal card sheet along individual card outlines of the plurality of individual cards.Type: GrantFiled: June 20, 2018Date of Patent: August 16, 2022Assignees: Kona I Co., Ltd., Kona M Co., Ltd.Inventors: Ki Sung Nam, Han Seon Kim, Suk Ku Lee
-
Patent number: 11411351Abstract: A separable and reconnectable connector for semiconductor devices is provided that is scalable for devices having very small contact pitch. Connectors of the present disclosure include signal pins shielded by pins electrically-coupled to ground. Embodiments provide one or more signal pins in a contact array electrically-shielded by at least one ground pin coupled to a ground plane. Embodiments thereby provide signal pins, either single-ended or a differential pair, usable to transmit signals with reduced noise or cross-talk and thus improved signal integrity. Embodiments further provide inner ground planes coupled to connector ground pins to shield pairs of differential signal pins without increasing the size of the connector. Inner grounding layers can be formed within isolation substrates incorporated into connector embodiments between adjacent pairs of signal pins.Type: GrantFiled: December 27, 2020Date of Patent: August 9, 2022Assignee: GITech, Inc.Inventor: John Williams
-
Patent number: 11395412Abstract: The disclosure relates to systems and methods for using additive manufacturing techniques for fabricating ball grid array (BGA) surface mounting pads (SMP), and surface mounted technology devices (SMT) package sockets. More specifically, the disclosure relates to additive manufacturing methods for additively manufactured electronic (AME) circuits such as a printed circuit board (PCB), and/or flexible printed circuit (FPC), and/or high-density interconnect printed circuit board (HDIPCB) each having integrated raised and/or sunk BGA SMP, and or surface mounting sockets for SMT device(s) defined therein, and methods of coupling surface mounted devices such as BGA and/or SMT thereto.Type: GrantFiled: April 8, 2020Date of Patent: July 19, 2022Assignee: Nano Dimension Technologies, LTD.Inventors: Daniel Sokol, Aviram Lancovici
-
Patent number: 11370174Abstract: A printer pressing assembly for forming material layers is provided. The printer pressing assembly includes a support assembly having a support surface, a driver and a press stop. The driver is able to change an elevation of the support surface relative to an elevation of the press stop. A nozzle is capable of dispensing a material onto the support surface. Further, a press is positionable opposite to the support surface and capable of moving relative to the support. Additionally, the press stop is capable of being elevated above the support surface so as to engage an abutment surface of the press to set a pre-determined distance between the contact surface of the press and the support surface.Type: GrantFiled: December 30, 2019Date of Patent: June 28, 2022Assignee: IO Tech Group Ltd.Inventors: Michael Zenou, Ziv Gilan