Assembling Bases Patents (Class 29/830)
-
Patent number: 11372392Abstract: A computer-implemented method of internally printing a biostructure on a damaged area of a patient. The method includes: assembling a first bioprinter capsule and a first cartridge capsule to form an assembled bioprinter internally within the patient based, at least in part, on directing one or more magnetic fields towards a first bioprinter capsule and a first cartridge capsule, moving the assembled bioprinter to the internally damaged area of the patient based, at least in part, on altering the one or more external magnetic fields directed towards the assembled bioprinter, and printing, via the assembled bioprinter, a first biostructure onto the internally damaged area of the patient based, at least in part, on altering the one or more external magnetic fields directed towards the assembled bioprinter, wherein the one or more external magnetic fields are sequentially altered to incrementally move the assembled bioprinter along at least one plane.Type: GrantFiled: September 18, 2020Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: Sarbajit K. Rakshit, Mukundan Sundararajan
-
Patent number: 11369049Abstract: An electromagnetic shielding element and, transmission line assembly and electronic structure package using the same are provided. The electromagnetic shielding element is applied to the transmission line assembly and the electronic structure package to shield electromagnetic noise. The electromagnetic shielding element includes a quantum well structure, and the quantum well structure includes at least two barrier layers and at least one carrier confined layer located between the two barrier layers. Each barrier layer has a thickness between 0.1 nm and 500 nm, and the thickness of the carrier confined layer is between 0.1 nm and 500 nm. The electromagnetic shielding element absorbs electromagnetic wave noise to suppress electromagnetic interference.Type: GrantFiled: June 21, 2019Date of Patent: June 21, 2022Assignee: HOTEK MATERIAL TECHNOLOGY CO., LTD.Inventors: Hao-Wei Fong, Ming-Goo Chien, Chia-Yu Wu
-
Patent number: 11357108Abstract: A printed circuit board connector for orthogonal mating of two or more printed circuit boards. The connector utilizes interior perimeter trace connections of a main printed circuit board and internal trace connections of a mating printed circuit board in conjunction with external trace connections. The main board may utilize surface connections, where both external trace connections and internal trace connections are exposed on a surface of the main board to couple to the mating board. The main board may include a slot or pocket, allowing for the partial insertion of the mating board into the main board, with internal trace connections disposed within the slot or pocket. The slot or pocket may extend through the main board, such that the internal trace connections are disposed along a side of the pocket to couple with corresponding internal trace connections of the mating board.Type: GrantFiled: October 25, 2021Date of Patent: June 7, 2022Assignee: Battelle Memorial InstituteInventors: Andrew M. Schimmoeller, Jeffrey A. Friend
-
Patent number: 11352297Abstract: The invention provides novel methods and novel additive compositions and use thereof in a wide range of concrete production for improving properties of concrete materials, such as durability and aestheticity. The methods and compositions of the invention may be applied in a variety of cement and concrete components in the infrastructure, construction, pavement and landscaping industries.Type: GrantFiled: March 22, 2018Date of Patent: June 7, 2022Assignee: SOLIDIA TECHNOLOGIES, INC.Inventors: Ahmet Cuneyt Tas, Deepak Ravikumar, Jason E. Bryant
-
Patent number: 11350530Abstract: A process for producing a backplane circuit board (20) having an internal face (142) adapted to be connected to connectors (13) of circuit boards (12) and an external face (143) adapted to be connected to an external connector (15), blind holes (146, 148) opening on the internal face (142) and external face (143) of the backplane circuit board (20), wherein bonding layers (31, 32) having zones (41, 42) cleared of material facing the blind holes are used between the printed circuits (21, 22, 23).Type: GrantFiled: December 19, 2019Date of Patent: May 31, 2022Assignee: SAFRAN ELECTRONICS & DEFENSEInventors: François Guillot, Patrice Chetanneau
-
Patent number: 11345790Abstract: Described herein are techniques for reducing resin squeeze-out including a method comprising receiving a first component and a second component, where the first component is configured to be joined to the second component at an overlap area using an adhesive layer to form a structure having a ledge. The method further comprises applying the adhesive layer to the overlap area on the first component. The method further comprises selectively curing a portion of the adhesive layer adjacent to the ledge. The method further comprises forming the structure by combining the first component, the second component, and the adhesive layer and curing a remainder of the adhesive layer.Type: GrantFiled: August 13, 2019Date of Patent: May 31, 2022Assignee: International Business Machines CorporationInventors: Sarah K. Czaplewski-Campbell, Eric J. Campbell
-
Patent number: 11329029Abstract: A semiconductor package includes a first semiconductor chip including a first chip body portion and a first chip rear bump disposed in a region recessed into the first chip body portion, and a second semiconductor chip stacked on the first semiconductor chip and including a second chip body portion and a second chip front bump protruding from the second chip body portion. The first chip rear bump includes a lower metal layer and a solder layer disposed on the lower metal layer. The second chip front bump is bonded to the solder layer. The second chip front bump is disposed to cover at least the solder layer on a bonding surface of the second chip front bump and the solder layer.Type: GrantFiled: August 19, 2020Date of Patent: May 10, 2022Assignee: SK hynix Inc.Inventor: Sung Ho Cho
-
Patent number: 11272620Abstract: The present disclosure relates to the technical field of circuit boards, and provides an embedded circuit board and a method for manufacturing the embedded circuit board. The embedded circuit board includes: a first outer wiring board, a base board, and a second outer wiring board. The base board has at least one groove, the first outer wiring board, the base board and the second outer wiring board define through holes to form a resonant chamber. A minimal distance between the side walls of the groove and the side walls of the adjacent through holes is 50 um-400 um. An electronic device is received in the groove.Type: GrantFiled: December 27, 2020Date of Patent: March 8, 2022Assignee: SHENNAN CIRCUITS CO., LTD.Inventors: Lixiang Huang, Zedong Wang, Hua Miao
-
Patent number: 11266013Abstract: A rigid-flex printed circuit board includes an inner circuit substrate, two adhesive sheet layers formed on the inner circuit substrate, two shielding structures, and two outer circuit layers. The inner circuit substrate is divided into a flexible area, a first and second rigid area. Each shielding structure includes a copper layer, a metal seed layer formed on the copper layer, a flexible dielectric layer formed on the metal seed layer, and a backing adhesive sheet layer formed on the flexible medium layer. The backing adhesive sheet layer is pressed on the adhesive sheet layer and the inner circuit substrate located in the flexible area. Each outer circuit layer is formed on the copper layer, located in the first rigid area and the second rigid area and electrically connected to the inner circuit substrate.Type: GrantFiled: September 23, 2020Date of Patent: March 1, 2022Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.Inventor: Wei-Xiang Li
-
Patent number: 11251171Abstract: Embodiments may relate to a substrate for use in a system in package (SIP). The substrate may include a first couple to couple with a first component via a permanent couple such that the first component is communicatively coupled with a bridge. The substrate may further include a second couple to removably couple with an interposer such that the interposer is communicatively coupled with the bridge via a communicative couple. Other embodiments may be described or claimed.Type: GrantFiled: June 13, 2018Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Michael Rifani, Robert J. Munoz, Thomas P. Thomas, John Mark Matson, Kursad Kiziloglu
-
Patent number: 11234325Abstract: A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.Type: GrantFiled: June 20, 2019Date of Patent: January 25, 2022Assignee: Infinera CorporationInventors: Aneesh Kachroo, Mithun Gopal V V, Navneeth Jayaraj
-
Patent number: 11219128Abstract: A laminated structure includes an interconnect structure including first and second product areas and a first interconnect layer, and a first insulating layer formed on the interconnect structure. The first product area includes an opening penetrating the first insulating layer, and the second product area includes an annular groove penetrating the first insulating layer. The laminated structure further includes an electronic component mounted inside the opening in the first product area with an annular gap formed between the electronic component and a wall surface defining the opening, an insulating member located inside the groove in the second product area, a second insulating layer that fills the annular gap and the groove, and covers the first insulating layer, the electronic component, and the insulating member, and a second interconnect layer formed on the second insulating layer, and electrically connected to the first interconnect layer.Type: GrantFiled: August 3, 2020Date of Patent: January 4, 2022Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Izumi Tanaka
-
Patent number: 11212914Abstract: The present disclosure provides a circuit board, including a substrate on which a first conductive layer and an electronic device are disposed, wherein the first conductive layer is disposed on a first surface of the substrate, and wherein a bottom end of the electronic device is disposed on the first conductive layer through the substrate. The present disclosure provides a display device.Type: GrantFiled: April 24, 2019Date of Patent: December 28, 2021Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xingjun Shu, Jianwu Wu, Xi Chen, Xinda Li, Shengwei Yang, Yadong Zhang, Jianye Tang, Jiaqiang Wang
-
Patent number: 11191164Abstract: A mold includes a mold base material and a rugged structure located at a main surface of the mold base material. The rugged structure includes a plurality of linearly shaped projected portions for forming wiring, and a circularly shaped projected portion for forming a pad portion, in which a light-shielding layer is provided at a top portion flat surface of the circularly shaped projected portion for forming the pad portion.Type: GrantFiled: September 26, 2016Date of Patent: November 30, 2021Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Ryohei Kasai, Tadashi Furukawa, Ryo Furugen, Teppei Sotoda, Tetsushi Hosoda, Ayako Furuse
-
Patent number: 11191159Abstract: A printed circuit board connector for orthogonal mating of two or more printed circuit boards. The connector utilizes interior perimeter trace connections of a main printed circuit board and internal trace connections of a mating printed circuit board in conjunction with external trace connections. The main board may utilize surface connections, where both external trace connections and internal trace connections are exposed on a surface of the main board to couple to the mating board. The main board may include a slot or pocket, allowing for the partial insertion of the mating board into the main board, with internal trace connections disposed within the slot or pocket. The slot or pocket may extend through the main board, such that the internal trace connections are disposed along a side of the pocket to couple with corresponding internal trace connections of the mating board.Type: GrantFiled: February 19, 2021Date of Patent: November 30, 2021Assignee: BATTELLE MEMORIAL INSTITUTEInventors: Andrew M. Schimmoeller, Jeffrey A. Friend
-
Patent number: 11178757Abstract: A process of manufacturing a multiple-layer printed circuit board includes selectively applying a dielectric resin to a region of a circuitized core layer. The process also includes partially curing the dielectric resin prior to performing a lamination cycle to form the multiple-layer printed circuit board that includes the circuitized core layer.Type: GrantFiled: July 6, 2018Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Bruce J. Chamberlin, Matthew S. Kelly, Scott B. King, Joseph Kuczynski
-
Patent number: 11152296Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.Type: GrantFiled: July 23, 2018Date of Patent: October 19, 2021Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD.Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
-
Patent number: 11116071Abstract: In a printed circuit board (1), thermal vias (19) are formed between the lower surface (A) and an upper surface (B) of the substrate plate (10) of the printed circuit board through the steps of: applying a respective solder resist mask (21, 31) to the lower surface (A) and the upper surface (B); applying solder to the lower surface (A) and reflow soldering the solder, wherein the solder penetrates into the boreholes (20) and forms convex menisci (26) protruding beyond the edge (22) of the respective boreholes on the lower surface (A); and creating regions (35) on the upper surface (B), which are freed from solder resist material, and which are intended for contacting at least one electronic component (17) on the upper surface and each of which comprise at least one of the thermal vias. Subsequently, the upper surface (B) can be provided with electrical components (17) on these regions (35).Type: GrantFiled: October 8, 2018Date of Patent: September 7, 2021Assignee: ZKW Group GmbHInventor: Erik Edlinger
-
Patent number: 11109489Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.Type: GrantFiled: August 15, 2019Date of Patent: August 31, 2021Assignee: RAYTHEON COMPANYInventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
-
Patent number: 11092551Abstract: A method for fabricating a surface enhancement of Raman scattering substrate is disclosed. The method further includes patterning a hardmask on a portion of a substrate. The method further includes directionally etching a portion of an exposed portion of the substrate to form a first stepped portion. The method further includes trimming the hardmask laterally to a first predetermined width. The method further includes directionally etching a portion of exposed horizontal portions of the substrate to form a second stepped portion.Type: GrantFiled: October 17, 2019Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Chanro Park, Ruilong Xie, Juntao Li
-
Patent number: 11086023Abstract: A global navigation satellite system (GNSS) receiver can include a code generator, a signal correlator circuit, and a processor. The code generator can generate samples of a plurality of ranging codes associated with corresponding GNSS transmitters. The signal correlator circuit can receive, according to a first clock rate, samples of a signal from a GNSS transmitter, and update, according to a second clock rate and a time division multiplexing scheme, cross-correlation values indicative of cross-correlations between the signal and a subset of the plurality of ranging codes. The second clock rate can be equal to at least multiple times the first clock rate. The signal correlator circuit can determine final results of the cross-correlation values based on the updating of the cross-correlation values, and a processor can identify the GNSS transmitter among the plurality of GNSS transmitters based on the final results of the cross correlation values.Type: GrantFiled: May 22, 2018Date of Patent: August 10, 2021Assignee: Rockwell Collins, Inc.Inventors: John E. Acheson, Thomas V. Dewulf
-
Patent number: 11062984Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.Type: GrantFiled: November 1, 2018Date of Patent: July 13, 2021Assignee: Micron Technology, Inc.Inventors: Tzung-Han Lee, Yaw-Wen Hu, Neng-Tai Shih, Hsu Chiang, Hsin-Chuan Tsai, Sheng-Hsiung Wu
-
Patent number: 11058009Abstract: A method of manufacturing a component carrier is disclosed. The method includes forming a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; patterning a front side of the stack using a first photo-imageable dielectric; and patterning a back side of the stack. A component carrier is also disclosed.Type: GrantFiled: November 20, 2019Date of Patent: July 6, 2021Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventor: Jeesoo Mok
-
Patent number: 11032908Abstract: Discovered is a daughter circuit board for direct connection to another mother circuit board. The daughter circuit board has an edge electrode for conductive connection to a surface pad on the mother board. An opening in the daughter circuit board can be aligned with the surface pad on the mother circuit board. The opening can contain solder which when reflowed can establish a bond between the daughter circuit board and the surface pad on the mother circuit board.Type: GrantFiled: November 1, 2019Date of Patent: June 8, 2021Assignee: UOP LLCInventor: Sreenivasu Balusu
-
Patent number: 10991557Abstract: Disclosed herein is a reaction chamber comprising a cavity, an upper electrode disposed in the cavity, a gas diffusion plate, and an adjustment assembly, wherein the gas diffusion plate is disposed directly above the upper electrode, and blocks the cavity, and the gas diffusion plate is provided with a plurality of air holes; the adjustment assembly is disposed on the gas diffusion plate.Type: GrantFiled: November 13, 2018Date of Patent: April 27, 2021Assignee: HKC Corporation LimitedInventor: Huailiang He
-
Patent number: 10983647Abstract: A method for manufacturing a touch panel includes the steps of: forming a first imprint layer; forming a first wire forming groove portion; forming a first wire; forming a spacer layer so that the spacer layer is placed over a surface of the first imprint layer in which the first wire forming groove portion has been formed and overlaps a part of the first wire; forming a second imprint layer so that the spacer layer is sandwiched between the first imprint layer and the second imprint layer; forming a second wire forming groove portion; forming a second wire; and delaminating the spacer layer from the first imprint layer and removing, together with the delaminated portion, a portion of the second imprint layer that overlaps the delaminated portion.Type: GrantFiled: August 3, 2018Date of Patent: April 20, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Mikihiro Noma, Takatoshi Kira
-
Patent number: 10980113Abstract: A circuit board structure that includes a resin-based conductive adhesive layer is disclosed, in which a conductive layer is arranged between a first circuit board and a second circuit board. The conductive layer includes a first conductive paste layer and the resin-based conductive adhesive layer is formed on the first conductive paste layer. The resin-based conductive adhesive layer contains a sticky resin material and a plurality of conductive particles distributed in the sticky resin material. The plurality of conductive particles establish an electrical connection between the first conductive paste layer and the resin-based conductive adhesive layer.Type: GrantFiled: May 15, 2019Date of Patent: April 13, 2021Assignee: Advanced Flexible Circuits Co., Ltd.Inventors: Kuo-Fu Su, Chih-Heng Chuo, Gwun-Jin Lin
-
Patent number: 10964633Abstract: A wiring substrate includes: a wiring layer; an insulating layer covering the wiring layer, and including a first opening portion exposing the wiring layer and a second opening portion exposing the wiring layer, wherein a diameter of the second opening portion is larger than that of the first opening portion; a first metal layer formed in the first opening portion and the second opening portion, and having a recess in the second opening portion; and a second metal layer that is formed on the first metal layer formed in the first opening portion and the second opening portion, wherein a portion of the second metal layer fills the recess. The first metal layer and the second metal layer serve as connection terminals to be electrically connected to an electronic component.Type: GrantFiled: April 20, 2020Date of Patent: March 30, 2021Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Hikaru Tanaka
-
Patent number: 10954119Abstract: A MEMS micromirror includes a mirror surface driving structure which is positioned on a substrate and includes two L-shaped structures in head-to-tail arrangement. Each L-shaped structure includes a second torsion beam, an L-shaped transverse plate and a second comb-shaped structure. The first driving electrode is provided on the substrate at a position under a head end of the L-shaped transverse plate, the head end of the L-shaped transverse plate is rotatable with support of the second torsion beam, and a tail end of the L-shaped transverse plate is connected with the second comb-shaped structure. The micromirror surface layer is disposed above the mirror surface driving structure, the first torsion beam is fixed by the substrate and supports two sides of the micromirror surface layer, and two sides, corresponding to the second comb-shaped structures, of the micromirror surface layer are provided with first comb-shaped structures, respectively.Type: GrantFiled: August 19, 2020Date of Patent: March 23, 2021Assignee: INSTITUTE OF GEOLOGY AND GEOPHYSICS CHINESE ACADEMY OF SCIENCES (IGGCAS)Inventors: Hang Li, Chen Sun, Lianzhong Yu
-
Patent number: 10950463Abstract: A method of manufacturing a component carrier is disclosed. The method includes providing an electrically insulating layer structure having a front side and a back side, wherein the front side is covered by a first electrically conductive layer structure and the back side is covered by a second electrically conductive layer structure, carrying out a first opening process, such as a first laser drilling, through the first electrically conductive layer structure and into the electrically insulating layer structure from the front side to thereby form a blind hole in the electrically insulating layer structure, and thereafter carrying out a second opening process, such as a second laser drilling, through the second electrically conductive layer structure and through the electrically insulating layer structure from the back side to thereby extend the blind hole into a through hole, in particular a laser through hole, with substantially trapezoidal shape.Type: GrantFiled: January 31, 2019Date of Patent: March 16, 2021Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventor: Abderrazzaq Ifis
-
Patent number: 10874018Abstract: A printed wiring board includes a laminate including first conductor pads on first surface side of the laminate and second conductor pads on second surface side of the laminate, and a solder resist layer formed on the first surface side of the laminate and having openings formed such that the openings are exposing the first conductor pads respectively. The laminate includes a resin insulating layer and has first surface on the first surface side and second surface on the second surface side on the opposite side with respect to the first surface of the laminate, and the second conductor pads are embedded in the second surface of the laminate such that the second conductor pads have surfaces exposed from the second surfaces of the laminate respectively and that the surfaces of the second conductor pads are protruding from the second surface of the laminate.Type: GrantFiled: July 3, 2019Date of Patent: December 22, 2020Assignee: IBIDEN CO., LTD.Inventors: Teruyuki Ishihara, Hiroyuki Ban, Haiying Mei
-
Patent number: 10873145Abstract: Aspects of the embodiments are directed to a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements. In embodiments, the PCB is part of a dual inline memory module. The conductive layer can be fashioned such that it extends out from the PCB and returns over the circuit elements to define an air gap between the conductive layer and the surface of the PCB and/or the surface of the circuit elements. In embodiments, a connection adaptor can be used to accommodate various PCB thicknesses so that the PCB can be electrically connected to an edge connector.Type: GrantFiled: December 29, 2016Date of Patent: December 22, 2020Assignee: Intel CorporationInventors: Guoliang Ying, Na Chen, Liguang Du
-
Patent number: 10839537Abstract: A camera module with a fixed near field focus is configured to capture a single image. That single image is segmented by an image divider a number of regions. A focus metric determiner then determines a focus metric for each of the regions. A depth map generator maps the focus metric into a depth value for each of the regions and combines the depth values to generate a depth map.Type: GrantFiled: May 10, 2016Date of Patent: November 17, 2020Assignee: STMicroelectronics (Research & Development) LimitedInventor: Duncan Hall
-
Patent number: 10798841Abstract: An electronic apparatus includes a housing, a first substrate, and at least one substrate module. The housing includes side plates and a bottom plate. The side plates define the inside space having a bottom opening. The side plates include a first side plate and a second side plate connected to the first side plate. The first side plate has a protrusion protruding toward the inside space of the housing. The bottom plate is connected to the side plates to close the bottom opening. The first substrate is provided in the inside space to face the bottom plate. The at least one substrate module is provided on the first substrate in the inside space. The substrate connecting member is provided on the first substrate to face the second side plate and has a hole into which the protrusion of the first side plate is inserted.Type: GrantFiled: August 13, 2019Date of Patent: October 6, 2020Assignee: KABUSHIKI KAISHA YASKAWA DENKIInventor: Takashi Fujiki
-
Patent number: 10764995Abstract: A method for fabricating a substrate structure is provided, which includes the steps of: disposing at least a strengthening member on a carrier; sequentially forming a first circuit layer and a dielectric layer on the carrier, wherein the strengthening member is embedded in the dielectric layer; forming a second circuit layer on the dielectric layer; removing the carrier; and forming an insulating layer on the first circuit layer and the second circuit layer. The strengthening member facilitates to reduce thermal warping of the substrate structure.Type: GrantFiled: January 11, 2018Date of Patent: September 1, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Jin-Wei You, Chun-Lung Chen
-
Patent number: 10749414Abstract: A motor driving device that converts alternating-current power to direct-current power and drives a motor, the motor driving device including a printed circuit board having a first plate surface and a second plate surface, having an inverter module and an inverter module provided on the first plate surface, having a first power pattern provided on the second plate surface and connected to the inverter module, having a second power pattern provided on the second plate surface and connected to the inverter module, and having a jumper portion to connect the first power pattern and the second power pattern. A cross-sectional area of the jumper portion is larger than a cross-sectional area of the first power pattern or the second power pattern.Type: GrantFiled: April 27, 2016Date of Patent: August 18, 2020Assignee: Mitsubishi Electric CorporationInventors: Norikazu Ito, Takuya Shimomugi, Masahiro Fukuda
-
Patent number: 10691232Abstract: A pressing pad for assembling a display module by applying a pressure to a flexible display panel to attach the flexible display panel to a window member and a method of assembling a display module, the pressing pad including a first pressing part that applies a first pressure onto a display area of the flexible display panel; a second pressing part that applies a second pressure onto a pad area of the flexible display panel, the second pressure being less than the first pressure and the pad area of the flexible display panel being adjacent to the display area of the flexible display panel; and a support part that supports the first and second pressing parts, wherein the second pressing part has a height from the support part that is less than a height of the first pressing part.Type: GrantFiled: January 11, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jun Namkung, Yonghoon Won, Yonghoon Chun
-
Patent number: 10681812Abstract: A flexible connector includes a unitary connector block having first and second board-facing areas. The first and second board-facing areas are longitudinally spaced from each other on a chosen surface of the connector block. The connector block includes a block body transversely separating the chosen surface from an opposing surface oppositely facing from the chosen surface. The connector block includes a flexible connector bridge longitudinally interposed between the first and second board-facing areas. A first connector port is located within the first board-facing area. A second connector port is located within the second board-facing area. A connector trace extends through at least a portion of the block body between the first and second board-facing areas. The connector trace electrically connects the first and second connector ports. Methods of making and using the flexible connector are also included.Type: GrantFiled: June 12, 2019Date of Patent: June 9, 2020Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventor: Jeffrey David Hartman
-
Patent number: 10672693Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.Type: GrantFiled: April 3, 2018Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
-
Patent number: 10665452Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.Type: GrantFiled: June 26, 2018Date of Patent: May 26, 2020Assignee: ASM IP Holdings B.V.Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
-
Patent number: 10651526Abstract: A flexible flat cable and a manufacturing method thereof are provided. The flexible flat cable includes a plurality of ground parts comprising a conductive material disposed at intervals, a plurality of signal transmission parts comprising a conductive material disposed between the plurality of ground parts, an outer skin covering the signal transmission parts and the ground parts, and a conductive adhesive layer disposed between the ground parts and the signal transmission parts and the outer skin part, the signal transmission part comprising an insulating member and a strip line disposed within the insulating member and the ground part comprising a ground member having the same cross section as the strip line and a conductive adhesive block coupled to the ground member with the conductive adhesive layer.Type: GrantFiled: June 22, 2017Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-hee Bae, Young-kun Kwon
-
Patent number: 10631406Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.Type: GrantFiled: June 8, 2016Date of Patent: April 21, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Chih-Cheng Lee
-
Patent number: 10531577Abstract: A method of manufacturing a component carrier is provided. The method includes forming a through hole between a first main surface and a second main surface of an electrically insulating layer structure by removing material from at least one of the main surfaces of the electrically insulating layer structure, in particular by irradiating at least one of the main surfaces of the electrically insulating layer structure with at least one laser shot, wherein the at least one main surface from which material is removed, in particular which is to be irradiated, is not covered by an electrically conductive layer structure at least in a surface region in which the through hole is to be formed, and subsequently at least partially filling the through hole and at least partially covering the main surfaces of the electrically insulating layer structure by an electrically conductive filling medium.Type: GrantFiled: July 3, 2019Date of Patent: January 7, 2020Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventor: Gernot Grober
-
Patent number: 10511076Abstract: An RF coupler having: a pair of input ports; a pair of output ports; and a coupling region for coupling: a portion of an input signal at a first one of the input ports to first of the pair of output ports and another portion of the input signal fed to the first one of the input ports a second one of the output ports; and one portion of an input signal fed to a second one of the input ports to the second of the pair of output ports and another portion of the input signals fed to the second one of the input ports to the second one of the output ports. The coupling region comprises a plurality of serially connected, vertically stacked, coupling sections. Each one of a plurality of electrically conductive layers is disposed between a pair of the vertically stacked coupling sections.Type: GrantFiled: September 1, 2017Date of Patent: December 17, 2019Assignee: Raytheon CompanyInventors: Christopher M. Laighton, Susan C. Trulli, Elicia K. Harper
-
Patent number: 10497667Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.Type: GrantFiled: March 26, 2018Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Xin-Hua Huang, Kuan-Liang Liu, Kuo Liang Lu, Ping-Yin Liu
-
Patent number: 10453787Abstract: An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.Type: GrantFiled: May 20, 2016Date of Patent: October 22, 2019Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.Inventors: Maurice S. Karpman, Nicole S. Mueller, Gary B. Tepolt, Russell Berman
-
Patent number: 10283492Abstract: Laminated interposers and packages, with embedded trace interconnects are provided. An example process for making an interposer or package achieves vertical conductive vias in the package by depositing conductive traces on multiple wafers or panes, then laminating these substrates into a stack, thereby embedding the conductive traces. The laminated stack is sliced to dimensions of an interposer or electronic package. A side of the sliced stack is then used as the top of the interposer or package, rendering some of the horizontally laid traces into vertical conductive vias. The interposer or package can be finished or developed by adding redistribution layers on the top and bottom surfaces, and active and passive components. Electronic components can also be embedded in the laminated stack. Some of the stack layers can be active dies, such as memory controllers, memory storage arrays, and processors, to form a memory subsystem or self-contained computing device.Type: GrantFiled: June 20, 2016Date of Patent: May 7, 2019Assignee: Invensas CorporationInventor: Nader Gamini
-
Patent number: 10274998Abstract: The invention relates to a holding component with a riser card for receiving an expansion component for a computer system. The riser card comprises a first mating plug connector on a first side of a bottom plate of the holding component. Further, the riser card comprises a first plug connector on a second side of the bottom plate opposite the first side. The holding component is adapted to receive the expansion component by establishing a plug connection of a second plug connector of the expansion component and the first mating plug connector on the holding component, wherein the holding component comprises a slot bracket, which is adapted to receive a slot angle of the expansion component. Furthermore, the invention relates to a support component for receiving at least one holding component and to an assembly comprising a chassis of a server module and of a holding component as well as of a support component.Type: GrantFiled: March 2, 2017Date of Patent: April 30, 2019Assignee: FUJITSU LIMITEDInventor: Ronny Hesse
-
Patent number: 10256117Abstract: There is provided a method for manufacturing a wiring substrate with a through electrode, the method including providing a device substrate having a through hole, an opening of the through hole being blocked by a current supply path and the wiring substrate including the device substrate as a core layer with the through electrode; and disposing a first metal in the through hole to form the through electrode by electroplating, in a depth direction of the through hole, using the current supply path.Type: GrantFiled: April 25, 2016Date of Patent: April 9, 2019Assignee: Sony CorporationInventors: Shun Mitarai, Shusaku Yanagawa, Hiroshi Ozaki
-
Patent number: 10231345Abstract: Embodiments of the present invention provide an attachment apparatus and an attachment method for a conductive adhesive. The attachment apparatus includes: a carrier stage, which is provided with at least one working surface, the working surface being configured to support a printed circuit board and provided with a groove, and the groove being provided with a plurality of adsorption holes on its bottom surface; a vacuum adsorption device being connected to each of the plurality of adsorption holes; and an attaching mechanism provided above the carrier stage, and configured to attach the conductive adhesive to a predetermined region of the printed circuit board, and the predetermined region being a region of the printed circuit board to be squeeze connected to a flexible printed circuit board or a chip on film.Type: GrantFiled: March 6, 2017Date of Patent: March 12, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Hanwei Tu, Minghui Liu, Hongjie Ding, Xikui Hao, Pengcheng Wang