With Selective Destruction Of Conductive Paths Patents (Class 29/847)
  • Patent number: 11890719
    Abstract: In a method of polishing a silicon wafer, a final polishing step includes an upstream polishing step and a subsequent finish polishing step. In the upstream polishing step, as a polishing agent, a first alkaline aqueous solution containing abrasive grains with a density of 1×1014/cm3 or more is first supplied, and the supply is then switched to a supply of a second alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×1013/cm3 or less. In the finish polishing step, as a polishing agent, a third alkaline aqueous solution containing a water-soluble polymer and abrasive grains with a density of 5×10?13/cm3 or less is supplied. Thus, the formation of not only PIDs but also scratches with small depth can be suppressed.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 6, 2024
    Assignee: SUMCO CORPORATION
    Inventor: Shuhei Matsuda
  • Patent number: 11855027
    Abstract: An article of manufacture comprises: an integrated circuit having a contact; a conductive bump electrically coupled to the contact, the conductive bump having a profile with a wave pattern; a lead frame electrically coupled to the conductive bump; and an integrated circuit package mold, the integrated circuit package mold covering portions of the conductive bump and the lead frame.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: December 26, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jose Daniel Carlos Torres, Ruby Ann Merto Camenforte
  • Patent number: 11648766
    Abstract: A method of making a metal foil heater comprising transferring a line image of a heater circuit to cutter and cutting the foil into a metal foil construction before affixing plastic sheets to both sides while attaching wires configured to supply current to the heater.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: May 16, 2023
    Inventor: Jahn Jeffery Stopperan
  • Patent number: 11582872
    Abstract: A circuit board with conductive wiring which is precisely shaped and sized includes a two-part conductive element, namely a first conductive wiring layer and a second conductive wiring layer, a first cover film and a second cover film. The first conductive wiring layer and the second conductive wiring layer are in direct contact to each other. A projection of the first conductive wiring layer and a projection of the second conductive wiring layer along a direction perpendicular to the circuit board overlap with each other. The first and the second cover films wrap the first and the second conductive wiring layers, respectively.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 14, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Ke-Jian Wu, Fang-Bo Xu, Peng Wu, Jian-Quan Shen
  • Patent number: 11517238
    Abstract: Provided are methods of making a long-term implantable electronic device, and related implantable devices, including by providing a substrate having a first encapsulation layer that covers at least a portion of the substrate, the first encapsulation layer having a receiving surface; providing one or more electronic devices on the first encapsulation layer receiving surface; and removing at least a portion of the substrate from the first encapsulation layer; thereby making the long-term implantable electronic device. Further desirable properties, including device lifetime increases during use in environments that are challenging for sensitive electronic device components, are achieved through the use of additional layers such as longevity-extending layers and/or ion-barrier layers in combination with an encapsulation layer.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: December 6, 2022
    Assignees: NORTHWESTERN UNIVERSITY, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: John A. Rogers, Hui Fang, Jianing Zhao, Enming Song, Yoon Kyeung Lee
  • Patent number: 11233498
    Abstract: Disclosed is a Bragg mirror, a resonator and a filter device comprised thereof. The Bragg mirror comprises a stack of plurality of layers arranged in an axial direction, wherein the plurality of layers comprises at least one first layer comprising, in a radial direction, a first material and a second material, wherein the first material is a first metal and the second material is a different material with respect to the first material, and wherein the first material is radially embedded by the second material in the first layer, or vice versa. The resonator comprises a top electrode, a bottom electrode, a piezo electric layer arranged between the top electrode and the bottom electrode, a substrate, and a Bragg mirror arranged between the bottom electrode and the substrate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 25, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Arto Turo Ilmari Nurmela, Jian Gu, Xiang Wei
  • Patent number: 11145613
    Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 11125713
    Abstract: A sensor for the detection of analyte includes a substrate, a working electrode and counter electrode formed on a surface of the substrate, and an antibody bioconjugated to a surface of an exposed portion of the working electrode.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 21, 2021
    Assignee: CASE WESTERN RESERVE UNIVERSITY
    Inventors: Chung Chiun Liu, Yifan Dai
  • Patent number: 11120171
    Abstract: A computing device has a processor. A display is coupled to the processor. A user interface is coupled to the processor for entering data into the computing device. A memory is coupled to the processor, the memory storing program instructions that when executed by the processor, causes the processor to: display a floorplan of a blueprint file, wherein the blueprint file is a non-CAD file; select a scale factor for the floorplan; mark and label at least one electrical panel; generate wire routes from selected points on the floorplan to a desired electrical panel of the at least one electrical panel, wherein generating wire routes comprises generating a straight line path from one of the selected points to the desired electrical panel when a direct route is selected; and generate a cost for each of the wire routes generated.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 14, 2021
    Assignee: MCCORMICK SYSTEMS LLC.
    Inventors: Todd McCormick, Ed Riggers
  • Patent number: 11106966
    Abstract: A controllable resistive element and methods for controlling the resistance of the same include a resistor layer formed in contact with a shared read/write electrode and a read electrode, the resistor layer having a resistivity that depends on a concentration of charge carrier ions. An electrolyte layer is formed on the resistor layer. A reservoir layer is formed on the electrolyte layer and in contact with a write electrode.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel P. de Souza, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 10720729
    Abstract: A method of making a lead for a stimulation device includes forming at least one pre-electrode in the shape of a ring, the at least one pre-electrode comprises at least two thin-walled portions separated by at least two thick-walled portions; disposing the at least one pre-electrode near a distal end of a lead body; joining at least one conductor to each thick-walled portion of the at least one pre-electrode; and grinding the lead body and the at least one pre-electrode to remove the thin-walled portions of the at least one pre-electrode to form segmented electrodes from the thick-walled portions of the at least one pre-electrode.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: July 21, 2020
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventor: Anne Margaret Pianca
  • Patent number: 10664112
    Abstract: A touch module and a manufacturing method thereof, and a touch screen are provided. The method of manufacturing a touch module includes: forming a composite electrode, a lead, and a lead pad each of which has a stacked structure of a transparent conductive layer and a metal layer on a substrate by one patterning process, the touch module including a touch area, and a peripheral area and a bonding area located at the periphery of the touch area, the composite electrode being formed in the touch area, the lead being formed in the peripheral area, and the lead pad being formed in the bonding area; forming a protective layer outside the touch area, and etching away the metal layer of the composite electrode to form a transparent touch electrode.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: May 26, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shouzheng Wu, Qing Zhang, Jun Xu, Fusheng Huang, Heng Zhang, Ji Shao, Dapeng Liu, Zhigang Ouyang, Baoqing Yin, Xiaojun Wang, Tongmin Liu
  • Patent number: 10509322
    Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
  • Patent number: 10271146
    Abstract: Techniques described herein generally include methods and systems related to a speaker device comprises a planar oscillation element configured to generate an ultrasonic acoustic signal, a shutter element, a first comb drive, and a second comb drive. The shutter element is configured to cover an opening that is positioned to receive the ultrasonic acoustic signal to modulate the ultrasonic acoustic signal such that an audio signal is generated. The first comb drive is coupled to the shutter element and configured to displace the shutter element in a first direction and the second comb drive is coupled to the shutter element and configured to displace the shutter element in a second direction.
    Type: Grant
    Filed: February 8, 2014
    Date of Patent: April 23, 2019
    Assignee: Empire Technology Development LLC
    Inventor: Mordehai Margalit
  • Patent number: 10021785
    Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes a first circuit layer disposed on an upper surface of a substrate, an insulating layer disposed on the substrate and the first circuit layer, a second circuit layer disposed on an upper surface of the insulating layer, and a via configured to connect between the first circuit layer and the second circuit layer, and a lower part of the via is in contact with the upper surface of the substrate.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: July 10, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung-Sam Kang, Young-Gwan Ko, Sang-Hoon Kim, Kang-Wook Bong, Hye-Won Jung, Yong-Wan Ji
  • Patent number: 9724896
    Abstract: A copper heat dissipation material having a satisfactory heat dissipation performance is provided. The copper heat dissipation material has an alloy layer containing at least one metal selected from Cu, Co, Ni, W, P, Zn, Cr, Fe, Sn and Mo on one or both surfaces, in which surface roughness Sz of the one or both surfaces, measured by a laser microscope using laser light of 405 nm in wavelength, is 5 ?m or more.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: August 8, 2017
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Hajime Momoi, Satoru Morioka, Toshiyuki Ono, Hideta Arai, Ryo Fukuchi, Atsushi Miki
  • Patent number: 9402574
    Abstract: Disclosed herein is a sensor comprising a conduit; the conduit comprising an organic polymer; a working electrode; the working electrode being etched and decorated with a nanostructured material; a reference electrode; and a counter electrode; the working electrode, the reference electrode and the counter electrode being disposed in the conduit; the working electrode, the reference electrode and the counter electrode being separated from each other by an electrically insulating material; and wherein a cross-sectional area of the conduit that comprises a section of the working electrode, a section of the reference electrode and a section of the counter electrode is exposed to detect analytes.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: August 2, 2016
    Assignees: THE UNIVERSITY OF CONNECTICUT, BIORASIS
    Inventors: Liangliang Qiang, Santhisagar Vaddiraju, Fotios Papadimitrakopoulos
  • Patent number: 9380709
    Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiung Hsu, Huang-Yu Chen, Tsong-Hua Ou, Wen-Hao Chen
  • Patent number: 9345132
    Abstract: The present invention discloses a package substrate layout design to achieve multiple substrate functions for engineering development and verification. The substrate layout contains a connection structure to connect to a plurality of power/ground domains on the package substrate. With different combination of the cutting lines on the package substrate, the invention can achieve multiple substrate functions without impacting the customer's PCB or system board design and provide cost effective and fast cycle time for engineering development phase.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 17, 2016
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yu-Ru Chang, Yu-Fang Hsia, Ling-Chih Chou
  • Patent number: 9307651
    Abstract: A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: April 5, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tsung-Yuan Chen, Shu-Sheng Chiang
  • Patent number: 9299649
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Cheng-Hsien Hsieh, Hsien-Pin Hu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9271387
    Abstract: A circuit board structure manufacturing method includes the following steps. A circuit substrate is provided including an insulating layer, a first metal layer, and a second metal layer. The insulating layer is disposed between the first metal layer and the second metal layer. The first metal layer has a first cavity. The insulating layer has a second cavity and a provisional region. A width of the first cavity is larger than a width of the second cavity. The provisional region is defined between a sidewall of the first metal layer defining the first cavity and another sidewall of the first metal layer defining the second cavity. A first masking layer is formed to cover the first metal layer and provisional region. The second cavity is exposed from the first masking layer. A heat-dissipating metal member is formed in the second cavity. Furthermore, the first masking layer is removed.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 23, 2016
    Assignee: Boardtek Electronics Corporation
    Inventors: Chien-Cheng Lee, Chung-Hsing Liao
  • Patent number: 9248275
    Abstract: One embodiment is a stimulation lead including a lead body comprising a longitudinal surface, a distal end, and a proximal end; and multiple electrodes disposed along the longitudinal surface of the lead body near the distal end of the lead body. The multiple electrodes include multiple segmented electrodes with each of the segmented electrodes having an exterior surface, an interior surface opposite the exterior surface, a proximal end, and a distal end. At least one of the segmented electrodes includes one or more of a) at least one channel formed in the segmented electrode and extending from the proximal end to the distal end of the segmented electrode, b) an arcuate groove formed in at least one of the distal end surface or the proximal end surface, or c) a notch formed in the segmented electrode and extending from the proximal end to the distal end of the segmented electrode.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: February 2, 2016
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Andrew DiGiore, Anne Margaret Pianca, Michael Adam Moffitt
  • Patent number: 9177832
    Abstract: A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Zigmund R. Camacho
  • Patent number: 9077344
    Abstract: Insulating substrates may be selectively removed to form electrical connections between conductive patterns on different faces of the insulating substrate or between conductive patterns on the insulating substrate and external circuits.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: July 7, 2015
    Assignee: Atmel Corporation
    Inventors: Carl Carley, David Brent Guard
  • Publication number: 20150101857
    Abstract: There is provided a method for manufacturing a printed circuit board including: preparing a substrate having a conductive layer formed on at least a portion thereof; forming an insulating layer formed with an opening through which a portion of the conductive layer is exposed on the substrate; forming a plating seed layer on the insulating layer and the exposed conductive layer; forming an electroplating layer on the plating seed layer by overplating the plating seed layer; and etching the overplated portion in a lump to form a circuit layer in the opening.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 16, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Da Hee KIM, Jung Hyun PARK, Yong Yoon CHO, Sung Won JEONG, Gi Ho HAN, Ki Hwan KIM
  • Patent number: 8997341
    Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: April 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshinori Ejiri, Kiyoshi Hasegawa, Takehisa Sakurai, Yoshiaki Tsubomatsu
  • Patent number: 8997343
    Abstract: A method for manufacturing multilayer printed circuit board includes step below. A metal substrate is provide, the metal substrate includes a number of substrate unit. A first insulating layer is formed on one surface of the metal substrate. The first insulating layer has a number of first through holes. An electrically conductive circuit is formed in each substrate unit. A second insulating layer is formed on the other surface of the metal substrate. The second insulating layer has a number of second through holes. A first metal cylinder is formed in a first through hole and a second metal cylinder is formed in a second through hole. The number of substrate units are folded and laminated, the connected and aligned first metal cylinder and the second metal cylinder communicates the electrically conductive circuits.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: April 7, 2015
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Chien-Pang Cheng
  • Publication number: 20150092356
    Abstract: A method for manufacturing a printed wiring board includes forming a removable layer over first pads in central portion of an interlayer insulation layer to mount IC chip, forming on the interlayer and removable layers a resin insulation layer having openings exposing second pads in peripheral portion of the interlayer layer to connect second substrate, forming a seed layer on the resin layer, in the openings and on the second pads, forming on the seed layer a plating resist having resist openings exposing the openings of the resin layer with diameters greater than the openings, filling the resist openings with electrolytic plating such that metal posts are formed in the resist openings, removing the resist, removing the seed layer exposed on the resin layer, and removing the removable layer and the resin layer on the removable layer such that cavity exposing the first pads is formed in the resin layer.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 2, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Kazuhiro YOSHIKAWA, Takashi Kariya
  • Publication number: 20150092377
    Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: JASON R. WRIGHT, Michael B. Vincent, Weng F. Yap
  • Patent number: 8991042
    Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Manabu Sakamoto, Tetsuya Shirasu, Naoki Idani
  • Publication number: 20150077963
    Abstract: A printed wiring board includes a wiring board, and multiple posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board. Each of the metal posts has a first surface connected to the wiring board, a second surface formed to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 19, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema ADACHI, Yuzo KAIDA
  • Patent number: 8978462
    Abstract: The invention relates to a submillimeter-sized hot-wire sensor (1) comprising a substrate (10), two support rods (11, 12), a metal wire (13) extending between the two ends of the support rods (11, 12), and electrical contacts (14, 15) disposed on the support rods, said contacts each being linked to one of the ends of the wire (13). The metal wire comprises at least two layers of metal materials, one of said layers being made of a material exhibiting a residual stress under tension and the other layer being made of a material exhibiting a residual stress under compression. The thicknesses of these metal layers are adapted so as to compensate the residual stresses between the various layers.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: March 17, 2015
    Assignees: Centre National de la Recherche Scientifique, Ecole Centrale de Lille
    Inventors: Philippe Jacques Pernod, Leticia Gimeno Monge, Abdelkrim Talbi, Alain Merlen, Romain Victor Jean Viard, Vincent Mortet, Ali Soltani, Vladimir Preobrazhensky
  • Publication number: 20150053466
    Abstract: A printed circuit board (PCB) and a method for manufacturing the PCB are disclosed. A PCB includes a transparent insulating substrate, a conductive circuit layer 16, and a transparent cover layer. The conductive circuit layer is located between the transparent insulating substrate and the transparent cover layer. The conductive circuit layer includes a first Ni—W alloy pattern layer, a copper pattern layer, and a second Ni—W alloy pattern layer. The first Ni—W alloy pattern layer is adhered with the transparent adhesive layer. Bottom surfaces of the conductive pattern layer are coated by the first Ni—W alloy pattern layer. Top surfaces and side surfaces of conductive pattern layer are coated by the second Ni—W alloy pattern layer.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Inventors: MING-JAAN HO, XIAN-QIN HU, JIAN LUO, FU-YUN SHEN
  • Publication number: 20150047977
    Abstract: The present invention provides an automatic encoding device including a first electrode, a second electrode, and a third electrode. The first electrode and the second electrode are connected through a connecting point, so that an electric parameter between the first electrode and the second electrode changes according to a parameter needing to be corrected. The present invention further provides a method for applying the automatic encoding device to various biosensors and a method for manufacturing the automatic encoding device. Positions and the number of contacts for connecting the automatic encoding device and a detection system are fixed. Therefore, connection sites on the detection system are effectively utilized. On the other hand, the automatic encoding device in the present invention can provide different parameter information by only changing the positions of the connecting points on the electrodes, the process is simple and stable, and the probability of human errors is reduced.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 19, 2015
    Inventors: Tao Liu, Huanxi Ge, Chia-Lin Wang, Yun Ye
  • Publication number: 20150047892
    Abstract: A printed circuit board (PCB) backdrilling method is disclosed, where a conductive layer is disposed between a surface of a PCB on an intended-for-backdrilling side of a plated through hole (PTH) and a target signal layer of the PCB, and the method includes: performing a first backdrilling on the PTH with a first preset depth starting from the surface of the PCB; controlling the backdrill bit to move along the drill hole formed in the first backdrilling toward the target signal layer; and when the backdrill bit is in contact with the conductive layer, completing a second backdrilling with a second preset depth starting from the conductive layer.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 19, 2015
    Inventors: Yongxing Yang, Feng Gao, Mingli Huang
  • Patent number: 8957319
    Abstract: Disclosed herein is a method for removing a seed layer in manufacturing a printed circuit board, the method including: forming a photo resist layer on a printed circuit board having a seed layer formed on a surface thereof; removing the photo resist layer according to a predetermined pattern; forming a plating layer for a circuit on the predetermined pattern from which the photo resist layer is removed; exposing the seed layer by removing the photo resist layer around the plating layer; forming a corrosion layer on surfaces of the seed layer and the plating layer by performing a chemical reaction of the substrate from which the seed layer is exposed in a reactor in which a predetermined gas is filled; and removing the seed layer by irradiating a laser on the corrosion layer to remove the corrosion layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Han, Yoon Su Kim, Kyoung Moo Harr, Kyung Seob Oh, Kyung Suk Shim, Du Sung Jung
  • Publication number: 20150040392
    Abstract: A PCB includes a base layer, a wiring pattern formed on a surface of the base layer, and a protecting layer formed on the wiring pattern. The protecting layer is formed by printing and solidifying an ink on the wiring pattern. The ink includes a cycloaliphatic epoxy resin, a phenoxyl resin solution, a solvent, a hardener, and an antifoaming agent.
    Type: Application
    Filed: August 12, 2014
    Publication date: February 12, 2015
    Inventors: MING-JAAN HO, XIAN-QIN HU, ZHI-TIAN WANG
  • Publication number: 20150033557
    Abstract: A method of producing a conductive path on a substrate including depositing on the substrate a layer of material having a thickness in the range of 0.1 to 5 microns, including metal particles having a diameter in the range of 10 to 100 nanometers, employing a patterning laser beam to selectably sinter regions of the layer of material, thereby causing the metal particles to together define a conductor at sintered regions and employing an ablating laser beam, below a threshold at which the sintered regions would be ablated, to ablate portions of the layer of material other than at the sintered regions.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: Orbotech Ltd.
    Inventors: Zvi KOTLER, Michael ZENOU
  • Patent number: 8943685
    Abstract: A method of manufacturing a capacitor-embedded printed circuit board using a first conductive layer formed on one side of an insulation layer, the method including: forming a second conductive layer on one side of the first conductive layer; forming a second electrode by removing a portion of the second conductive layer; forming a first electrode by removing a portion of the first conductive layer in correspondence with the second electrode; and forming a dielectric layer on one side of the second electrode.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: February 3, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Do Kweon, Sung Yi, Hong-Won Kim
  • Patent number: 8935850
    Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: January 20, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Masahiro Kaneko, Satoru Kose, Hirokazu Higashi
  • Publication number: 20150016087
    Abstract: A circuit board (1) for mounting at least one light source (10), comprising a substrate (2) and a plurality of printed electrical conductors (3) printed on the substrate (2), At least one printed electrical conductor (3) comprises a first region (4) for arranging the light sources (10). The circuit board (1) further comprises reflectors (5) which are disposed between the printed electrical conductors (3) adjacent to each other and cover other regions of the printed electrical conductors (3) than the first region (4), wherein the reflectors (5) are insulating reflectors. The circuit board is easy to manufacture, has relatively high reflective property, and can efficiently reflect the light emitted from the light source. Also disclosed are a method for manufacturing the circuit board, and an illumination device comprising the circuit board.
    Type: Application
    Filed: February 7, 2013
    Publication date: January 15, 2015
    Inventors: ChengCheng Feng, Xiaomian Chen, Chuanpeng Zhong, Hao Li
  • Patent number: 8931169
    Abstract: Methods of fabricating components for microelectronic devices are described herein. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. Bit line contact openings can be formed in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. A first conductive material is deposited into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate. Dielectric features can electrically insulate the conductive line.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh Dang Tang
  • Publication number: 20150008950
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2011
    Publication date: January 8, 2015
    Inventors: Roy E. Swart, Paul B. Fischer, Charlotte C. Kwong
  • Patent number: 8925191
    Abstract: In one embodiment, a method of fabrication of a stimulation lead comprising a plurality of segmented electrodes for stimulation of tissue of a patient, the method comprises: providing an elongated, substantially cylindrical substrate, the substrate comprising a plurality of recesses defined in an outer surface of the substrate; coating the substrate with conductive material; patterning conductive material on the substrate to form a plurality of electrode surfaces for at least the plurality of segmented electrodes and a plurality of traces connected to the plurality of electrode surfaces, wherein each electrode surface and its corresponding trace are defined in the recesses on the outer surface of the substrate and are electrically isolated from other electrode surfaces and traces; providing insulative material over at least the plurality of traces; and electrically coupling the plurality of traces to conductive wires of a lead body.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: January 6, 2015
    Assignee: Advanced Neuromodulation Systems, Inc.
    Inventors: John Swanson, Kevin Turner, Jerome Boogaard
  • Publication number: 20150005573
    Abstract: A device, including an implantable electronic circuit integrated at least one of in or on a substrate, wherein the device includes a hermetic enclosure having a space therein, wherein the substrate forms at least a portion of the hermetic enclosure.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 1, 2015
    Inventors: Torsten LEHMANN, Gregg Jørgen SUANING, Tony Mikael NYGARD, Thomas GUENTHER, William LIM, Kushal DAS
  • Patent number: 8918988
    Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mohammed Fazil Fayaz, Jeffery Burton Maxson, Anthony Kendall Stamper, Daniel Scott Vanslette
  • Publication number: 20140373350
    Abstract: The invention relates to a method for producing a circuit board involving the removal of a subregion thereof. In said method, at least two layers or plies of the circuit board (1) are interconnected, the subregion (6) to be removed is prevented from being connected to an adjacent ply of the circuit board by providing a layer (7) of adhesion-preventing or bonding-preventing material, and peripheral zones (8) of the subregion (6) to be removed are separated from adjoining zones of the circuit board (1). According to the invention, a fissure formation and/or a detachment from the subregion (6) of the circuit board (1) to be removed is initiated in a subregion in or on the layer (7) of adhesion-preventing or bonding-preventing material, and the subregion (6) to be removed is then removed, thus making it possible to remove a subregion (6) to be removed from a circuit board (1) in a simple and reliable, and if necessary automated, manner.
    Type: Application
    Filed: December 3, 2012
    Publication date: December 25, 2014
    Applicant: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Gerald Weidinger, Gregor Langer, Volodymyr Karpovych
  • Patent number: 8917495
    Abstract: Provided is a circuit board manufacturing method capable of securing circuit patterns on a plate-like insulator while keeping the relative position between the circuit patterns, and also provided is a circuit board in which the relative position between a plurality of circuit patterns is kept. A first coil (30) having one turn is formed in a planar shape from a metal plate. Next, a second coil (40) having four turns is formed in a planar shape from a metal plate, wherein both of the ends (41, 42) of the coil are linked to other adjacent regions via linking portions (43, 44). A pair of the first coil (30) and the second coil (40) are then overlapped so as to face each other through a plastic plate (50) in which a plurality of prepregs are stacked, after which the links by the linking portions (43, 44) are disconnected.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Hitoshi Shimadu, Takehiko Sawada, Tomoaki Asai, Ryou Yamauchi
  • Patent number: 8912447
    Abstract: A method includes patterning one or more electrical layers on a substrate; shaping the patterned substrate into a 3-dimensional contour, wherein the contour including a significant change in gradient in or adjacent to one or more sensing areas of the electrical layer, and over-molding the shaped substrate. Degradation of a trace in the electrical layer at or adjacent to the one or more sensing areas during shaping and/or over-molding is substantially minimized based on the width of the trace, the thickness or number of layers of the trace, the bending radius of the trace, the material of the trace, and/or a primer over layer on the trace.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 16, 2014
    Assignee: Fischer Technology Pte. Ltd.
    Inventors: Chee Seng Leong, Sze Lam Chua