Abstract: A method of manufacturing a circuit substrate includes forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method includes filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including Sn—Bi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further includes performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.

Abstract: A multilayer substrate includes an element assembly including a second insulating layer and a first insulating layer arranged in this order from a first side to a second side with respect to a layer stacking direction, a first conductor layer on the first side of the first insulating layer and including a plated layer, and a second conductor layer on the first side of the second insulating layer. The first conductor layer includes a first connection portion and a first circuit portion, and the second conductor layer includes a second connection portion and a second circuit portion. When viewed from the layer stacking direction, the first circuit portion includes an overlapping portion which overlaps the second circuit portion. A portion of the first connection portion connected to the second connection portion has a maximum thickness greater than a maximum thickness of the overlapping portion.

Abstract: A lighting system and a method of operating a lighting module are described. The lighting module includes a heat sink a first LED element mounted on the heat sink emits light as a low beam pattern. A second LED element mounted on the heat sink emits light as a high beam pattern. A driver circuit electrically connected to the first and second LED elements to selectively supply electrical power for operation. The driver circuit is disposed to operate in a first and a second mode. In the first mode, to provide a low beam illumination, the first LED element is operated in a high power state while the second LED element is turned off. In the second mode, to provide a high beam illumination, the second LED element is operated in a high power state, while the first LED element is operated in a dimmed state.

Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation with the mold forming part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects.

Abstract: A method of forming a multi-layer circuit on a curved substrate includes forming, by a laser direct structuring process, a first layer of the multi-layer circuit on a first surface of the curved substrate. The method includes applying a first layer of paint to the first layer of the multi-layer circuit. The method includes forming, by the laser direct structuring process, a second layer of the multi-layer circuit on the first layer of the paint and electrically coupled to the first layer of the multi-layer circuit. The method includes applying a second layer of paint over the second layer of the multi-layer circuit and forming, by the laser direct structuring process, a third layer of the multi-layer circuit on the second layer of the paint and electrically coupled to the second layer of the multi-layer circuit.

Abstract: Methods and systems for making a multi-layer circuit board are disclosed, including electrically connecting a boring device with a plated multi-layered circuit board; cutting a first bore having a first diameter through a first layer of the plated multi-layered circuit board; reciprocally extending a second cutting device a first predetermined distance into a barrel plated multi-layered circuit board and retracting the cutting device a second predetermined distance that is less than the first predetermined distance to form a second bore; after each retraction, sensing for electrical contact indicating a closed circuit between the cutting device and the plated multi-layered circuit board; if a closed circuit is sensed, determining if the second bore has reached an expected depth of a contact layer; and if the expected depth of the contact layer has not been reached, determining that a sliver has been formed in the barrel.

Abstract: A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.

Abstract: Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Abstract: A circuit board includes a circuit substrate, a solder, and a surrounding portion. The circuit substrate includes a connecting pad. The solder is formed on a surface of the connecting pad. The surrounding portion is formed on the surface of the connecting pad and cooperates with the connecting pad to form a groove receiving the solder. The surrounding portion surrounds the solder and is spaced from the solder. A method for manufacturing a circuit board is also provided.

Abstract: The present disclosure relates to systems and methods using thermal vias to increase the current-carrying capacity of conductive traces on a multilayered printed circuit board (PCB). In various embodiments, parameters associated with vias may be selected to control various electrical and thermal properties of the conductive trace. Such parameters include the via diameter, a plating thickness, a number of vias, a placement of the vias, an amount of conductive material to be added or removed from the conductive trace, a change in the resistance of the conductive trace, a change in a fusing measurement of the conductive trace, and the like.

Abstract: A multilayer PCB structure includes a core layer, a first layer on a first surface of the core layer, a second layer on a second surface of the core layer, and a thermally conductive material in the core layer. The first surface and the second surface of the core layer are opposite to each other, and a window is formed on the second layer by removing part of the second layer. The window of the second layer exposes part of the core layer below the thermally conductive material.

Abstract: Disclosed is a printed circuit board (PCB) module including a first PCB comprising a base PCB, a sidewall disposed on a periphery of the base PCB, and conductive vias penetrating the sidewall, a second PCB disposed on the sidewall to cover a cavity formed by the sidewall of the first PCB, and at least one electronic component disposed inside the cavity and located on the first PCB and/or the second PCB, wherein the sidewall comprises a first layer disposed on an upper face of the base PCB and constructed of an insulating member, a second layer disposed on the first layer and comprising a polyimide, a third layer disposed on the second layer and constructed of an insulating member, and a fourth layer disposed on the third layer and comprising a conductive member conductive with respect to the conductive vias.

Abstract: A printed circuit board includes a printed wiring board, a semiconductor element, and conductive members. The printed wiring board includes an insulative substrate having a first surface and a second surface opposite to the first surface, and wiring provided on the second surface of the insulative substrate to face the through-holes. The insulative substrate has flexibility and through-holes passing through the insulative substrate from the first surface to the second surface. The semiconductor element is mounted on the first surface of the insulative substrate of the printed wiring board and has element terminals interposed between the printed wiring board and the semiconductor element. The conductive members filled in the through-holes connect the element terminals and the wiring.

Abstract: The present disclosure provides a flexible circuit board. The flexible circuit board includes a substrate; a conductive layer, disposed on the substrate; and a cover layer, disposed on a side of the conductive layer facing away from the substrate. The flexible circuit board is provided with a through hole penetrating through the flexible circuit board in the thickness direction. The cover layer includes a hollowed-out region located at least at an edge of one side of the through hole. The conductive layer includes an electrostatic discharge section exposed in the hollowed-out region.

Abstract: Solution casting a nanostructure. Preparing a template by ablating nanoholes in a substrate using single-femtosecond laser machining. Replicating the nanoholes by applying a solution of a polymer and a solvent into the template. After the solvent has substantially dissipated, removing the replica from the substrate.

Abstract: A power supply comprises a main circuit board and a multilayer power transmission board electrically coupled to the main circuit board. The multilayer board includes a conductive neutral layer having an inner side, a conductive line layer having an inner side facing the inner side of the conductive neutral layer, and a dielectric medium positioned between the conductive neutral layer and the conductive line layer. The power supply also comprises a first conductive outer layer positioned adjacently to an outer side of the conductive neutral layer, a second conductive outer layer positioned adjacently to an outer side of the conductive line layer, and a conductive plating material positioned within a slot formed in the multilayer power transmission board and covering an interior portion of the multilayer power transmission board facing the slot. The conductive plating material electrically couples the first and second conductive outer layers.

Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.

Abstract: The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.

Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Abstract: An insulator for a bus connector arrangement including a first layer defining at least one first aperture, a first annular protrusion emanating from the first layer at one first aperture, a second layer defining at least one second aperture configured to align with each of the at least one first apertures, and at least one second annular protrusion emanating from the second layer at each of the at least one second apertures.

Abstract: A method for making a redistribution circuit structure provides a substrate and forms a peelable layer on the substrate. A metal layer is formed on a surface of the peelable layer, the metal layer including a controlling circuit including at least two spaced units. A first photoresist layer is formed on a portion of the surface of the peelable layer and an insulating layer is applied to completely cover the first photoresist layer and the controlling circuit. Through holes are defined in the insulating layer to partially expose the controlling circuit and a seed layer applied on the insulating layer. A block layer is laid to divide the seed layer into multiple sections and electroplating in each section on a portion of the seed layer is applied to form a plating layer with better uniformity of thickness across all sections.

Abstract: A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.

Abstract: A probe card assembly is provided as follows. A tile fixing substrate is disposed on a printed circuit board. A plurality of ceramic tiles is detachably attached to the tile fixing substrate. Each of the plurality of ceramic tiles comprises a plurality of probes. A plurality of alignment marks is fixed to the tile fixing substrate.

Abstract: A manufacturing method of a circuit board includes the following steps. A conductive plate is provided. The conductive plate is patterned to form ducts. The patterned conductive plate is laminated with a core dielectric layer. The lamination leaves exposed a bottom surface of the patterned conductive plate. Through holes are opened in portions of the core dielectric layer within the ducts. A conductive material is formed in the through holes and over the core dielectric layer to produce a metallization layer electrically insulated from the patterned conductive plate. Dielectric layers and conductive layers are alternately stacked on an upper surface of the core dielectric layer. The conductive layers are electrically connected to the metallization layer.

Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.

Abstract: Creating in-via routing with a light pipe is disclosed. A resist layer is applied over a layer of conductive material provided in a via. A light pipe is inserted into the via. The surface of the light pipe includes at least one masked portion and at least one unmasked portion. A portion of the resist layer is exposed with light emitted from the unmasked portions of the light pipe. Portions of the conductive layer corresponding to the exposed portion of the resist layer are then removed to create the in-via routing.

Abstract: A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.

Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

Abstract: A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.

Abstract: A method includes forming one or more cores, wherein each of the one or more cores has a cross section corresponding to a conductor to be subsequently formed, forming an insulator around the one or more cores, removing the one or more cores to expose one or more recesses within the insulator, and forming one or more conductors in at least one of the one or more recesses of the insulator such that the cross sections of the one or more conductors conform to an interior surface of the one or more recesses in the insulator.

Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.

Abstract: A manufacturing method of a flexible transparent circuit includes preparing a circuit template. The method further includes using a flexible transparent polymer material to prepare a cured transparent carrier on the circuit template, wherein the cured transparent carrier has a groove circuit structure. The method includes coating a solution containing a conductive material in a groove of the cured transparent carrier. The method further includes forming a circuit with the high transparency and conductivity after the solvent is volatilized. The circuit are designed and manufactured according to the requirements, and the precision thereof is able to achieve the micron or nanometer level. The formed circuit is light. The circuit can be stretched, bended or twisted many times. The circuit has a good biological compatibility. The circuit manufactured by such method is expected to be applied in various fields such as smart contact lens, flexible transparent electron devices, electronic skins.

Abstract: A radio frequency identification (RFID) tag that includes an antenna having a spiral form disposed on a major surface of a flexible substrate is described. The RFID tag includes a first terminal disposed at a first end of the antenna and a second terminal disposed at the second end of the antenna. The RFID tag may include a pad portion along the length of the antenna between the first and second ends for mounting an integrated circuit. Except for the pad portion, a radius of curvature of the antenna along at least 90 percent of a length of the antenna between the first and second ends is greater than about 0.1 mm and less than about 10 mm.

Abstract: An electrical connection method of a printed circuit includes overlapping a base material and a thin member in which a thin conductor is mounted, forming a through hole which passes through the base material overlapped with the thin member in the overlapping and reaches the thin conductor of the thin member, and forming a printed circuit on the base material by a screen printing method using conductive paste. The through hole formed in the forming of the through hole is filled with the conductive paste in the forming of the printed circuit.

Abstract: A circuit board film-plated against corrosion of conductive traces comprises a substrate, a conductive circuit layer attached to the substrate, a plating film attached to outer surface of the conductive circuit layer, and a covering film. Each plating film comprises a top outer surface and a side surface. The circuit board defines at least one through hole. Each through hole passes through substrate, conductive circuit layer, and the plating film. The covering film covers the conductive circuit layer, the side surfaces, and the through holes. The conductive circuit layer and the side surfaces of the plating films are sealed against the atmosphere and cannot be corroded. A method for making the circuit board is also provided.

Abstract: A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.

Abstract: A method for producing an electrical wiring member includes press-molding a composition containing a resin material and metal particles with an insulating layer, each of which is constituted by a metal particle and a surface insulating layer covering the metal particle and containing a glass material as a main material, thereby obtaining a powder-compacted layer and irradiating the powder-compacted layer with an energy beam, thereby causing the irradiated regions to exhibit electrical conductivity.

Abstract: An in-cell touch screen and a display device are provided. In the in-cell touch screens, an insulation layer, in an area that each self-capacitance electrode overlap a wire, is provided with at least a first hole that runs through the insulation layer and each self-capacitance electrode is electrically connected with a corresponding wire via a corresponding first via hole; each self-capacitance electrode, within an area overlapping other wire than the corresponding wire and at a position corresponding to the first via hole, is disposed with a second via hole that runs through the self-capacitance electrode. An orthogonal projection of a second via hole on a lower substrate covers an orthogonal projection of a first via hole on the lower substrate. The in-cell touch screen can solve a problem of uneven image display due to nonuniform distribution of via holes in an insulation layer.

Abstract: A semiconductor structure comprises: a substrate, an alignment mark, pillars, and a seal wall. The alignment mark is adjacent to a surface of the substrate. The pillars protrudes from the substrate. The seal wall protrudes from the surface of the substrate and surrounding the alignment mark. The seal wall is between the pillars and the alignment mark. The pillars is configured into at least two different groups with different average heights. The seal wall around the alignment mark can prevent the alignment mark from the coverage of the flux. Further, the seal wall can be formed with pillars at the same time, and the increased cost is limited.

Abstract: A printed wiring board includes a base member that includes a ground wiring pattern and a printed wiring board reinforcing member bonded to the ground wiring pattern in a conductive state. The printed wiring board reinforcing member includes a metal base material layer and a nickel layer bonded to at least a surface on a side opposite to a side bonded to the ground wiring pattern of the metal base material layer by diffusion bonding.

Abstract: The steps of forming a multi-layer flexible printed circuit cable (flex circuit) with an electrical interconnection between independent conductive layers. In accordance with various embodiments, a partial aperture is formed in the flex circuit that extends through a first conductive layer and an intervening insulative layer to an underlying surface of a second conductive layer that spans the partial aperture. A solder material is reflowed within the partial aperture to electrically interconnect the first and second conductive layers.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

Abstract: A apparatus comprising a printed circuit board (“PCB”). The PCB comprises a first insulating layer and a second insulating layer. The first insulating layer is made of a first material and the second insulating layer is made of a second material. The first material has a lower dissipation factor than the second material. The first material and second material have substantially similar dielectric constants.

Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract: An interposer having a multilayered conductive pattern portion that is constructed by repeating the direct printing on a carrier of one or more conductive pattern layers and application of one or more insulating layers between the printed conductive pattern layers is described. Also, a method for manufacturing the interposer, a semiconductor package using the interposer, and a method for fabricating the semiconductor package are described.

Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate, and a through-hole conductor formed in the hole such that the conductor is connecting the first and second conductive layers. The conductor has a seed layer on inner wall of the hole, a laminated plated layer on the seed layer and a filled plated layer on the laminated layer, the laminated layer is formed such that the laminated layer is closing center portion of the hole and forming recess at end of the hole, the filled layer is formed such that the filled layer is filling the recess, and the laminated layer includes multiple electrolytic plated films laminated along the seed layer and each having thickness which is less at edge than at center.

Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.

Abstract: Conductive patterns and methods of using and printing such conductive patterns are disclosed. In certain examples, the conductive patterns may be produced by disposing a conductive material between supports on a substrate. The supports may be removed to provide conductive patterns having a desired length and/or geometry.

Abstract: An obfuscated radio frequency circuit may be manufactured to include a metallization layer, and a dielectric layer under the metallization layer. The dielectric layer may be made up of a plurality of dielectric substrates having different dielectric constants to obfuscate functions of the circuit.

Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.