With Encapsulating Patents (Class 29/855)
  • Patent number: 6970360
    Abstract: A tamper-proof enclosure for an electrical card, such as a high speed communications card, includes an enclosure in which the card is mounted. The enclosure has a wall with an opening, and a cup member is attached to the wall at the opening. A bus that is connected to the card extends through a passage in the cup member and through the opening in the wall. A security mesh is wrapped around the enclosure. The cup member is filled with liquid resin, which is also coated onto the security mesh. After the resin is cured, the resin in the cup member forms a plug that seals the security mesh from inner pressure when the enclosure is heated to an elevated temperature. The resin is preferably polyamide.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: November 29, 2005
    Assignee: International Business Machines Corporation
    Inventor: Arvind Kumar Sinha
  • Patent number: 6957475
    Abstract: A method of manufacturing a piezoelectric component includes forming an unhardened first elastic material partially on at least a pair of end portions of a piezoelectric element, the pair of end portions including an edge portion of the piezoelectric element, hardening the first elastic material, forming an unhardened second elastic material on the entire circumference of the piezoelectric element and the first elastic material, hardening the second elastic material, forming an unhardened outer-cladding resin on the entire circumference of the second elastic material covering the piezoelectric element and the first elastic material, and hardening the outer-cladding resin.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: October 25, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Morita, Masanobu Sugimori, Muneyuki Daidai
  • Patent number: 6948239
    Abstract: A method for fabricating a semiconductor apparatus using a board frame. A wiring board region of the frame includes an island on which a semiconductor device is mounted. A marginal region of the frame surrounds the wiring board region. A frame region is located around the marginal region. A support region extends between the wiring board region and the frame region to connect the wiring board region and frame region together through the support region. The marginal region is removed from the board frame and then put back to its original position, while maintaining the wiring board region connected to the frame region through the support region. Then, the device is mounted onto the island. Next, transfer-molding is performed on the device using a die set that includes a gate through which a thermosetting resin is guided into a cavity. Then, the marginal region is removed completely from the board frame.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: September 27, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takahiro Oka
  • Patent number: 6949470
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 27, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Patent number: 6941640
    Abstract: The present invention is directed to a miniature hard disc drive having a metal base plate, an actuator assembly wherein the actuator assembly comprises a plurality of bearings, a shaft, and a housing; a spindle motor assembly comprising a stator with conductors, a shaft, a plurality of bearings, and a rotor; and a monolithic body of phase change material unitizing said actuator assembly housing and stator to the base plate. Methods of developing and constructing the hard disc drive are also disclosed.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: September 13, 2005
    Assignee: Encap Motor Corporation
    Inventors: Griffith D. Neal, Dennis K. Lieu
  • Patent number: 6935020
    Abstract: A method of producing a battery-connecting plate by providing busbars which connect batteries together, attaching terminals to one end of wires to produce terminal-attached wires for detecting voltage of desired ones of the batteries, placing the terminal-attached wires in a predetermined layout in a wire protector, setting the busbars and wire protector in a mold with the burbars positioned corresponding to an arrangement of the batteries, injecting resin into the mold to produce a molded piece with the burbars and the terminal-attached wires therein, and cutting an element mount portion of each of the terminals and connecting a respective circuit protector element to the element mount portion in a bridging manner across the cut.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: August 30, 2005
    Assignee: Yazaki Corporation
    Inventor: Tomohiro Ikeda
  • Patent number: 6922890
    Abstract: A method is provided for planarization of structures which minimizes step heights, reduces process steps, improves cleanliness, and provides increased ease of debond. Structures are placed with working surfaces facing down onto an adhesive layer such that structures remain fixed during heating. A bi-layer encapsulating film is used to achieve planarization. A carrier is bi-laminated with a thermoplastic film layer followed by a chemically inert protective polymer film layer that can withstand etch and cleaning processes. The thermoplastic layer is laminated on top of the carrier; the polymer layer is laminated on top of the joined thermoplastic layer and carrier. The carrier with bi-layer film is then placed onto the backside of the structures to resist chemical attack from the front side during photostrip and enable planarization. When heat is applied, the bi-layer encapsulating film melts and pushes the polymer layer into the gaps between structures thereby achieving complete planarization.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: Qing Dai, Jennifer Qing Lu, Dennis Richard McKean, Eun Row, Li Zheng
  • Patent number: 6920688
    Abstract: A method of making an integrated circuit device using an encapsulated semiconductor die, having leads extending therefrom and attaching a heat spreader to each of the major outer encapsulant surfaces thereof, is disclosed. One or both of the heat spreaders has a pair of end posts configured for allowing further encapsulation of portions thereof and insertion into through-holes in a substrate to position and support the device during and following the outer lead solder reflow step at board assembly. The heat spreaders provide high heat dissipation and EMR shielding, and may be connected to the substrate ground to become ground planes.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: July 26, 2005
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6912781
    Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a set of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the conductors of the component are routed through the lead channels. A set of insertable lead terminals, adapted to cooperate with the specially shaped lead channels, are received and captured within the lead channels, thereby forming an electrical connection between the lead terminals and the conductors of the electronic component(s). A method of fabricating the device is also disclosed.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: July 5, 2005
    Assignee: Pulse Engineering, Inc.
    Inventors: Timothy J. Morrison, Aurelio J. Gutierrez, Thomas Rascon
  • Patent number: 6907656
    Abstract: A method for manufacturing thermal heads comprises providing a substrate having a first surface, a second surface opposite the first surface, heaters disposed on the first surface, and pairs of electrodes disposed on the first surface, the electrodes of each pair of electrodes being disposed in spaced-apart, confronting relation to each other. A driver IC is mounted on each of the electrodes. The driver ICs are then encapsulated with a resin. Grooves are formed in at least one of the first surface and the second surface of the substrate so that the electrodes of each pair of electrodes are disposed symmetrically with respect to one of the grooves. The substrate is then cut along the grooves to form individual thermal heads each having a heater, at least one of the driver ICs for providing a drive signal to drive the heater, and a sealing element formed by the resin for protecting the driver IC.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: June 21, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshiaki Saita, Osamu Takizawa
  • Patent number: 6904673
    Abstract: Ink jet printing apparatus is employed to form a non-polar ink stop line around a chip site on the polar surface of an organic laminate substrate. The non-polar ink stop line acts to confine polar liquid flux from spreading after application of the flux to the chip site prior to chip joining. Excessive flux spreading results in insufficient flux being present at the chip site for the formation of good electrical connections during solder reflow upon chip joining.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Julie Nadeau Filteau, Pierre M. Langevin, Robert L. Toutant, Alain Warren
  • Patent number: 6889426
    Abstract: A method for manufacturing wired circuit board that enables a wired circuit board of high quality to be manufactured without changing in dimension of the wired circuit board substantially. In this method, the wired circuit board is wound in layers in the winding process in such a manner that after an uncured thermosetting resin layer is formed on the wired circuit board in the resin layer forming process, a right-side spacer and a left-side spacer are disposed on the already wound wired circuit board at both widthwise ends thereof and also an upper spacer is disposed on the right-side spacer and the left-side spacer so as to cover a widthwise area of the wired circuit board, so that the right-side spacer, the left-side spacer and the upper spacer are positioned between the layers of the wired circuit board when wound. Thereafter, the wired circuit board wound in the rolled state is heated as it is, to cure the uncured thermosetting resin layer in the curing process.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: May 10, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Hirofumi Fujii, Shunichi Hayashi
  • Patent number: 6889429
    Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: May 10, 2005
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Phillip C. Celaya, James S. Donley, Stephen C. St. Germain
  • Patent number: 6889430
    Abstract: A method of selectively adjusting surface tension of a soldermask material. Specifically, a method of selectively adjusting the surface tension of a soldermask material to promote adhesion of a molding compound in a ball grid array package while maintaining a low surface tension on the ball attach area to prevent bridging between the solder balls. Solder balls require a low surface tension soldermask to minimize bridging, while the molding compound requires a high surface tension to provide adequate adhesion to the surface of the soldermask. By exposing selected portions of the soldermask to an activation method, such as ultra-violet radiation, the surface tension of the soldermask can be varied such that different areas of the package exhibit different surface tensions.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Partrick Tandy
  • Patent number: 6871388
    Abstract: A method of forming an electronic component includes laminating ceramic green sheets on a support film to obtain a ceramic green sheet laminate, forming through holes through the ceramic green sheet laminate at positions where via hole electrodes are to be located, applying conductive material into the through holes so as to fill the through holes and so as to be located on the upper surface of the ceramic green sheet laminate to form via hole electrodes, and sintering the ceramic green sheet laminate to form a substrate and so as to form protruding portions of the via hole electrodes which protrude upward from the upper surface of the substrate.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: March 29, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Ishino, Kenji Kubota, Tsuyoshi Saito, Michinobu Maesaka, Mamoru Ogawa, Jiro Inoue, Hiroaki Kaida
  • Patent number: 6867506
    Abstract: An apparatus for enclosing logic chips includes a substrate upon which a logic chip is mounted and a mold cap disposed upon the substrate and covering the logic chip. The mold cap includes at least one extension of sufficient size and shape to provide structural support to a corner section of the substrate.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: March 15, 2005
    Assignee: Intel Corporation
    Inventor: Joseph C. Barrett
  • Patent number: 6860004
    Abstract: In a method of manufacturing a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection, a sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: March 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
  • Patent number: 6860008
    Abstract: A method for producing fuel rails, which contain a hollow chamber that communicates with a fuel source via a connection. The fuel rail supplies fuel to a number of injection valves. At least one preassembled unit of an injection valve is integrated into the fuel rail by means of a materially adhesive connection during the production of the fuel rail and an electrical contacting of the individual injection valves is produced at the same time.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: March 1, 2005
    Assignee: Robert Bosch GmbH
    Inventors: Eckhard Bodenhausen, Franco Zeleny, Horst Kirschner
  • Patent number: 6848153
    Abstract: A method of manufacture of a surface acoustic wave device which includes a step of applying a photosensitive film resist on a substrate and forming a photosensitive film resist layer over at least a portion of a surface of the substrate; a step of forming acoustic absorbers only at the two sides orthogonal to the direction of the surface acoustic wave transmission; a step of placing in a package a surface acoustic wave element obtained by cutting and dividing the substrate and electrically connecting a connection electrode of the surface acoustic wave element with an external terminal of the package; and a step of sealing an opening of the package with a lid, wherein the main surface of the acoustic absorbers is formed parallel to the surface of the substrate.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: February 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shigeru Tsuzuki, Kunihiro Fujii, Masahiro Takada, Satoshi Matsuo, Takafumi Koga, Kozo Murakami
  • Publication number: 20040256148
    Abstract: An electronic circuit device has an electronic module that is deformed to match an installation location. The electronic module includes electronic parts and wires interconnecting the electronic parts. The electronic module is formed by mounting the electronic parts to the wires formed on a baseboard. After the baseboard is removed from the electronic module, the electronic module is deformed, and, thereafter, the configuration of the deformed electronic module is fixed.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 23, 2004
    Inventors: Takeuchi Yasutaka, Hironao Hayashi
  • Patent number: 6826829
    Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes fixing the die to the substrate, interconnecting the electronic die to an at least one bonding pad on the substrate to form an electrical connection, coating the interconnects and the electronic die with an electrically insulating coating, and covering the electronic die with a low temperature melting metal. Thus, the method of the present invention improves the reliability of the electronic die.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: December 7, 2004
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Cuong Van Pham, Jay DeAvis Baker, Mohan R. Paruchuri, Prathap Amervai Reddy, Vivek Amir Jairazbhoy
  • Publication number: 20040237299
    Abstract: To hermetically encapsulate a component applied to a carrier in the flip-chip style, it is proposed to initially cover this with a film applied sealed to the component and the carrier, to structure this, and to apply over this a hermetically sealing layer, in particular a metal layer, that hermetically terminates with the carrier.
    Type: Application
    Filed: July 22, 2004
    Publication date: December 2, 2004
    Inventors: Alois Stelzl, Hans Krueger, Gregor Feiertag, Ernst Christl
  • Patent number: 6823585
    Abstract: A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Mark J. LaPlante, Jon A. Casey, Thomas A. Wassick, David C. Long, Krystyna W. Semkow, Patrick E. Spencer, Robert A. Rita, Richard F. Indyk, Kathleen M. Wiley, Brian R. Sundlof, James Balz, Lori A. Maiorino, Donald R. Wall, Glenn A. Pomerantz
  • Patent number: 6823587
    Abstract: A method of making a data cable includes coupling an electrical conductor of an end of a cable to an electrical contact that is positioned within a portion of a connector housing. A protective clamp is positioned over a section of the cable rearwardly of the electrical contact. Another portion of the connector housing is formed over the cable section and the clamp, to thereby secure the cable with the connector housing. The protective clamp is positioned between the formed portion of the connector housing and the cable section and provides mechanical protection for the cable section to reduce damage thereto.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: November 30, 2004
    Assignee: Tensolite Company
    Inventor: Bruce Reed
  • Patent number: 6812068
    Abstract: In one aspect, the invention includes a method of encapsulating a semiconductor device, comprising: a) providing a semiconductor device; b) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor device; and c) dispensing a liquid encapsulating material through the plurality of orifices and over the semiconductor device. In another aspect, the invention includes a method of forming an electronic package, comprising: a) providing a circuit board having a circuit pattern; b) joining a plurality of semiconductor devices to the circuit board in electrical connection with the circuit pattern; c) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor devices; d) simultaneously dispensing liquid encapsulating material through at least two of the plurality of orifices and over at least two of the semiconductor devices; and e) curing the liquid encapsulating material.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: November 2, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Brand, Scott Gooch
  • Patent number: 6808950
    Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: October 26, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
  • Patent number: 6806559
    Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: October 19, 2004
    Assignee: Irvine Sensors Corporation
    Inventors: Keith D. Gann, Douglas M. Albert
  • Patent number: 6804883
    Abstract: A method for producing a pressure sensor, in which a semiconductor pressure pick-up is mounted on a mounting section of a lead grid, in particular a leadframe. The semiconductor pressure pick-up is electrically connected to contact sections of the lead grid. The lead grid, together with the semiconductor pressure pick-up, is inserted into an injection molding die. A die part is brought into contact at the side of the semiconductor pressure pick-up facing away from the mounting section or at side of the mounting section facing away from the semiconductor pressure pick-up. The semiconductor pressure pick-up in the injection molding die is subsequently enclosed by a housing made of mold compound. In order to prevent the mounting section from giving way, it is proposed to clamp the mounting section of the lead grid in the injection molding die when producing the housing.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: October 19, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Kurt Weiblen, Anton Doering, Juergen Nieder, Frieder Haag
  • Publication number: 20040187311
    Abstract: The present invention provides cables having a body that is surrounded by a vacuum metallized layer. The metallized layer can be grounded with a metallized thermoform connector to prevent the release or impingement of harmful EMI radiation. Optionally, an insulating top coating can be disposed over the metallized layer over the cable body.
    Type: Application
    Filed: October 21, 2003
    Publication date: September 30, 2004
    Applicant: Shielding for Electronics, Inc.
    Inventors: Jesus Al Ortiz, Rocky R. Arnold
  • Patent number: 6796024
    Abstract: According to the method of producing a semiconductor device, the substrate is provided with an opening formed at a substantially central position, interconnections and joining parts. The heat spreading plate has a fixed portion fixed to the substrate, a stage portion caved with respect to the fixed potion and connecting portions connecting the fixed portion and the stage portion. The heat spreading plate is fixed by positioning the stage portion at a position opposing the opening, then the heat spreading plate is welded to the substrate and the semiconductor chip is mounted on the stage portion through the opening. Then the semiconductor chip and interconnections formed on the substrate are electrically connected and sealing resin is formed on both sides of the heat spreading plate such that at least the semiconductor chip is sealed.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: September 28, 2004
    Assignee: Fujitsu Limited
    Inventors: Yoshitsugu Katoh, Mitsuo Abe, Yoshihiko Ikemoto, Sumikazu Hosoyamada
  • Patent number: 6779264
    Abstract: A method for manufacturing an electronic device by placing within a die a first lead with an element placement pad, a second lead, and an electronic element placed on the element placement pad. The electronic element, the element placement pad, a part of the first lead, and a part of the second lead are sealed in a package by injecting a sealing resin in the die from a position on a longer side of the package, with the position being offset toward one shorter side thereof. The first lead is bent in an S shape, with a bending depth being at least as large as the thickness of the first lead. A thickness of the resin on a non-device side of the element placement pad is smaller than the bending depth.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Kobayashi, Hideki Fukazawa, Satoshi Utsunomiya
  • Publication number: 20040148772
    Abstract: A method for packaging an injection-molded image sensor includes the steps of: providing metal sheets arranged in a matrix, each of the metal sheets having a first board, a second board and a third board to form a -shaped structure; performing a first injection molding process to encapsulate the metal sheets and to form a first molded body with the first to third boards exposed; performing a second injection molding process to form a second molded body and a cavity on the first molded body, wherein the first boards are located within the cavity; arranging a photosensitive chip having bonding pads within the cavity; providing wires for electrically connecting the bonding pads to the first boards, respectively; and arranging a transparent layer on a top of the second molded body to cover over the photosensitive chip.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Inventors: Jackson Hsieh, Jichen Wu
  • Patent number: 6769174
    Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: August 3, 2004
    Assignee: STMicroeletronics, Inc.
    Inventors: Harry M. Siegel, Anthony M. Chiu
  • Patent number: 6767767
    Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 27, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Tetsuya Hayashida, Norihiko Kasai
  • Patent number: 6764882
    Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: July 20, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Todd O. Bolken
  • Publication number: 20040128831
    Abstract: The described embodiments relate to methods and systems for forming die packages. In one exemplary embodiment, the method for forming die packages contacts interface areas of a die assembly to keep the interface areas free of an insulative material. The method distributes a flowable insulative material around portions of the die assembly.
    Type: Application
    Filed: December 19, 2003
    Publication date: July 8, 2004
    Inventors: Frank J. Bretl, Gary Powell, Donald L. Michael, Jefferson P. Ward, Joseph E. Scheffelin, Mohammad Akhavain
  • Patent number: 6757969
    Abstract: Method of fabricating LED assembly disclosed herein can provides a string of original colored high intensity LEDS usable for screen displaying or traffic signal lights molded by injecting harmless polyacrylic resin in a short time duration and at low temperature.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: July 6, 2004
    Inventor: Tsung-Wen Chan
  • Patent number: 6751858
    Abstract: In a method for manufacturing a sensor apparatus having a sensor chip disposed in a recess of a case, after the sensor chip is disposed in the recess of the case, an opening portion of the recess is closed with a sheet member. The sheet member can prevent foreign matters from intruding an inside of the recess during manufacturing steps. After that, a through hole is formed in the sheet member. Accordingly, the inside and outside of the recess communicate with each other, and the sensor chip can detect an external environment of the recess such as atmospheric pressure.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: June 22, 2004
    Assignee: Denso Corporation
    Inventors: Minoru Tokuhara, Yukihiro Kato
  • Patent number: 6743661
    Abstract: An apparatus and method for flexibly bonding an integrated circuit package to a printed circuit board are provided. The apparatus includes a semiconductor having first and second sides, where the first side defines an inner region and peripheral region. The inner region is surrounded by the peripheral region. An interposer having a substantially similar coefficient of thermal expansion to the semiconductor is included. A dielectric region surrounding the interposer is included. The dielectric region is configured to be partially elastic. A plurality of posts extends transversely through the dielectric region. The post have first and second ends where the first end is configured to be attached to the peripheral region of the semiconductor chip. The second ends of the posts are configured to be attached to an external assembly, wherein the posts are able to absorb stress due to a thermal expansion mismatch between the external assembly and the interposer.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: June 1, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: John Stephen Drewery
  • Patent number: 6742249
    Abstract: Method of manufacture of a composite wiring structure for use with at least one semiconductor device, the structure having a first conductive member upon which the semiconductor device can be mounted for electrical connection thereto. A dielectric member, made of ceramic or organo-ceramic composite material, is bonded to the first conductive member and contains embedded therein a conductive network and a thermal distribution network. A second conductive member may be incorporated with the composite wiring structure, with a capacitor electrically connected between the conductive network and the second conductive member. Bonding between the dielectric member and the conductive members may be in the form of a direct covalent bond formed at a temperature insufficient to adversely effect the structural integrity of the conductive network and the thermal distribution network.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: June 1, 2004
    Inventors: L. Pierre deRochemont, Peter H. Farmer
  • Patent number: 6740543
    Abstract: The present invention is a method and apparatus for encapsulating semiconductor dies and other devices using stencil printing techniques. The apparatus includes a pressurized vessel for containing encapsulation material, the apparatus having a head including a slot through which the encapsulating material escapes into the apertures of the stencil. The head is angularly adjustable relative to the stencil and thus relative to the streets between the semiconductor dies that are in the apertures of the stencil so that the head can be adjusted to the optimal angle for filling both the vertical and horizontal streets between the dies and minimizing the creation of voids in the encapsulant. The method involves encapsulating semiconductor dies using a pressurized stencil printing machine having a slot through which the encapsulating material is forced into the apertures in the stencil and wherein the slot is at a large angle relative to both the vertical and horizontal streets.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 25, 2004
    Assignee: Kulicke & Soffa Industries, Inc.
    Inventor: Claire Rutiser
  • Patent number: 6737300
    Abstract: A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: May 18, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi-Chuan Ding, Xin Hui Lee, Kun-Ching Chen
  • Patent number: 6735858
    Abstract: A method of manufacturing an electronic apparatus having a plastic housing. The method includes blow molding with a one-piece plastic housing around an electronic circuit board populated with components. The circuit board is fastened and held in-situ during the blow molding. Fastening locations are defined by contiguously sandwiched portions of the housing and the electronic circuit board.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: May 18, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventor: Harald Schmidt
  • Patent number: 6735860
    Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: May 18, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6733711
    Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: May 11, 2004
    Assignee: General Electric Company
    Inventors: Kevin Matthew Durocher, Ernest Wayne Balch, Vikram B. Krishnamurthy, Richard Joseph Saia, Herbert Stanley Cole, Ronald Frank Kolc
  • Publication number: 20040083606
    Abstract: Soldering of a first electrode and first circuit component, soldering of a second electrode and second circuit component, and hardening of an encapsulating resin are simultaneously performed by using the encapsulating resin which having a hardening accelerating temperature higher than a preheating temperature and equal to or lower than a main heating temperature.
    Type: Application
    Filed: October 8, 2003
    Publication date: May 6, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA.
    Inventors: Sadao Makita, Kuniyasu Hosoda
  • Patent number: 6730847
    Abstract: A connection protector kit for use with an electrical stub connection includes a flexible cap having first and second opposed ends and an interior wall defining a cavity. The first end is closed and an opening is formed in the second end and communicates with the cavity. A gel is disposed in the cavity. The cavity and the gel are adapted to receive the stub connection. Retaining means may be provided to retain the cap on the connection.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: May 4, 2004
    Assignee: Tyco Electronics Corporation
    Inventors: Frank J. Fitzgerald, Paul Raymond Carey, Rudolf Robert Bukovnik, Jeffery Craig Judd, Harry George Yaworski, Kenton Archibald Blue, Jimmy E. Marks, Sherif I. Kamel, George W. Pullium, III
  • Patent number: 6722030
    Abstract: A method is provided for manufacturing a saw filter in which a carrier plate 10 that can be separated into base plates 2 is respectively provided with interconnects in the base plate regions A and these are contacted to the active structures of SAW chips 1 in flip-chip technique. A metal foil 3 or plastic film 4 is placed onto the chip-equipped carrier plate 10 and, for example, is pressure and heat treated such that it envelopes each chip 1 (except for the chip surface facing toward the carrier plate 10) and lies hermetically tight on the carrier plate surface in regions between the chips.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: April 20, 2004
    Assignee: EPCOS AG
    Inventors: Alois Stelzl, Hans Krueger, Peter Demmer
  • Patent number: 6713321
    Abstract: A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: March 30, 2004
    Assignee: Siliconware Precision Industries Co. Ltd.
    Inventors: Chien-Ping Huang, Tzong-Dar Her
  • Publication number: 20040055155
    Abstract: System for providing an open-cavity semiconductor package. The system includes a method for wire bonding a finger sensor die to an external circuit. The finger sensor die includes a sensor array having one or more die contacts that are wire bonded to one or more external contacts of the external circuit so that a usable portion of the sensor array is maximized. The method comprises steps of forming a ball at a first end of a bonding wire, forming an electrically conductive connection between the ball and a selected external contact of the external circuit, extending the bonding wire to a selected die contact so as to form a wire loop having a low loop height, and forming an electrically conductive stitch connection between a second end of the bonding wire and the selected die contact.
    Type: Application
    Filed: August 20, 2003
    Publication date: March 25, 2004
    Inventor: Michael Manansala