Abstract: A fabrication method for an electronic device includes four steps. The first step is for preparing a leadframe with first and second conductive members. The second step is for connecting a first and a second electronic chips to the first and the second conductive members, respectively. For the third step, the first chip is enclosed by a first resin package allowing partial exposure of the first conductive member, while the second chip by a second resin package spaced from the first package. For the fourth step, the exposed part of the first conductive member is cut. The cutting is performed using first and second tools, where the first tool makes an indentation in the exposed part on a first side. On another side opposite to the first side, the second tool makes a full cut to be linked with the indentation.

Abstract: After conductive patterns are formed on the conductive foil every block by employing isolation trenches, conductive plating layers are arranged selectively on the conductive patterns. Therefore, it is possible to accomplish the circuit device manufacturing method by which the die bonding of the circuit elements can be applied stably and the wire bonding can also be applied stably and which can fit to the mass-production while saving the resource.

Abstract: Methods for attaching an integrated circuit die to a substrate. Specifically, substrates which are used for BOC/COB or F/C surface mounting comprise protrusions on the surface of the substrate. The protrusions are configured to form barriers to hold an adhesive paste within the barriers. An integrated circuit die is disposed on the top of the barriers and coupled to the substrate by the adhesive paste.

Abstract: A mold for taped lead frame assemblies is provided. The mold has a mold cavity large enough to hold an entire lead frame assembly. A taped lead frame assembly is placed completely in the mold cavity. A cover is used to cover the mold cavity. The cover is spaced apart from the taped lead frame assembly. A riser may be used to provide the spacing between the cover and the taped lead frame assembly, so that the cover does not contact the taped lead frame assembly. An encapsulation material is placed in the mold cavity and then hardened. The encapsulated taped lead frame assembly is then removed from the mold and singulated.

Abstract: A method and apparatus are provided for encapsulating a workpiece in a material having a lower melting temperature than that of the material for the workpiece to form an encapsulated block of standardized size and shape which may be mounted in a standardized fixture to facilitate machining on the workpiece. The invention includes both specialized molds for use in encapsulating a workpiece for various types of machining and systems for clamping and injecting encapsulant into such molds under pressure. After machining on a given side, a block is re-inserted in the appropriate mold and re-encapsulated to standardize size and shape for a subsequent machining operation. The process of machining and re-encapsulation are repeated until all sides of the workpiece requiring machining have been machined, at which time the encapsulant is removed from the workpiece, normally by being heated and melted.

Abstract: A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.

Abstract: The invention provides a method for processing leadframe items to form IC packages, each of the leadframe items comprising an IC carried by a suitable leadframe, the leadframe items being of two or more types. The method includes receiving the two or more types of leadframe items along respective input paths, moving at least two holders alternately between a processing region and a respective leadframe item reception position, each of the holders moving to the processing region and at a time when the other of the holders moves to its respective reception position, the reception positions being on respective ones of the input paths, each of the holders receiving leadframe items of the respective type at the respective reception position and delivering them to the processing region and encapsulating the ICs at the processing position.

Abstract: The invention relates to a method for the production of an MID device. Proceeding from a conductor track sheet, which comprises a support sheet as well as conductor tracks arranged thereon, a plastic body is injection-molded onto this conductor track sheet. The conductor tracks have a surface having numerous microscopically small projections and depressions and are designed so as to thereby produce a positively locking connection between the conductor tracks and the plastic body.

Abstract: A method of making a stacked assembly of integrated circuits (ICs) from prepackaged semiconductor chips is disclosed. The method involves the steps of first starting with a commercially available prepackaged semiconductor chip (e.g. a thin small outline package (TSOP)), that contains bare silicon die within an encapsulant and removing at least part of the encapsulant from the lateral sides to expose the wire bonds. More such prepackaged chips are modified and stacked upon one another. Metalization is performed on the stack to interconnect the layers. An additional embodiment discloses the use of lead frames to the stack of integrated circuits. Additional disclosure covers a method of stacking printed circuit boards (PCBs). A compact and low cost mini-computer is also disclosed that is made using methods of the present invention.

Abstract: The present invention provides a method for mounting a semiconductor element to a circuit board and a semiconductor device whereby connection reliability and connection strength in bonding of the semiconductor element and circuit board are enhanced and a connection resistance value is stabilized low. An insulating adhesive is applied to an opposite face of a circuit board. The circuit board is then connected with a semiconductor element by a conductive adhesive and the insulating adhesive which are interposed between an electrode on the circuit board and the projecting electrode and set in the same process. The circuit board and semiconductor element are connected by the insulating adhesive in addition to the conductive adhesive, so that connection reliability and connection strength are high and a connection resistance value is stabilized low.

Abstract: Method of making a proximity probe including providing a preform having an interior cavity accessible by an opened rearward end; coupling a coil to the preform proximate a forward most end of the preform for defining an assembly; locating a single support pin through the rearward end such that the support pin extends within the interior cavity while having an end emanating from the rearward end; cantilevering the emanating end between an upper and a lower mold plate defining a mold cavity for supporting the assembly; injecting moldable material into the mold cavity for molding an encapsulation of material over the assembly for defining an encapsulated probe tip, allowing the encapsulated probe tip to cure; removing the encapsulated probe tip from the mold cavity; removing the support pin from the assembly, and coupling a cable to the encapsulated probe tip for forming the proximity probe.

Abstract: A method for making an electrically shielded housing for an electrical device includes the steps of at least partially forming an insert member having a non-conductive outer surface portion and a conductive inner surface portion, insert molding the at least partially formed insert member in a cavity of a non-conductive housing body member so that the conductive inner surface portion of the insert member is disposed adjacent an outer surface portion of the body member cavity and the non-conductive outer surface portion of the insert member forms a housing cavity. An electrical device received in the housing cavity is electrically shielded by the conductive inner surface portion of the insert member and insulated from the conductive inner surface portion of the insert member by the non-conductive outer surface portion thereof.

Abstract: The invention is a method and apparatus for encapsulating semiconductor dies via stencil printing in which, after the dies have been stencil printed with encapsulant and prior to removal of the stencil from the dies, the edges of the encapsulating material are partially cured in order to prevent or minimize slump of the encapsulant in the time period between removal of the stencil and full curing of the encapsulant. In particular, the stencil can be provided with a plurality of light pipes that terminate at the edges of the apertures within which the dies are placed. Ultraviolet (UV) or other curing light is provided through the light pipes to the edges of the encapsulating material. Some general or localized heating can be provided to enhance or accelerate the light curing of the edges of the encapsulant, but without substantially curing the remainder of the encapsulating material.

Abstract: A method for attaching an electronic die to a substrate is disclosed. Preferably, the method includes fixing the die to the substrate, interconnecting the electronic die to an at least one bonding pad on the substrate to form an electrical connection, coating the interconnects and the electronic die with an electrically insulating coating, and covering the electronic die with a low temperature melting metal. Thus, the method of the present invention improves the reliability of the electronic die.

Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: The invention relates to an apparatus for processing electronic components, such as semi-conductor products, comprising at least two processing stations, at least one supply/discharge position for electronic components, a robot arm with engaging means for engaging the electronic components for displacing electronic components between the supply/discharge position and the processing stations, and a control for actuating the robot arm and the processing stations. The invention also relates to an assembly of at least two such apparatuses and to a method for processing electronic components which can be performed by means of the apparatus according to the invention.

Abstract: A method, and structure formed thereof, for processing an exposed conductive connection between an thermal inkjet head device and a flexible tape circuit connectable to control signals for driving the inkjet device. According to the method of processing, the exposed conductive connection is electrophoretically plated with a polymer to protect it against corrosive damage by coupling the exposed conductive connection to a first voltage potential and immersing it into an electrophoretic polymer solution in contact with an electrode at a second voltage potential thereby establishing a current between the electrode and the exposed connection such that the exposed connection is coated with a thin film of polymer of uniform thickness.

Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.

Abstract: A radio frequency identification tag is made with printed antenna coil integrated on a flexible substrate, and an integrated circuit area of the substrate adjacent the antenna coil for carrying circuit elements. The radio frequency identification tag is designed to be sufficiently robust to withstand the rigors of mail efficiency processing measurement applications.

Abstract: Where the length LD of a resin film forming region is, for example, 3 times as long as the pitch of the sprocket holes of the base film, the resin coating is performed by using 6 nozzles, and where the length LD is, for example, 6 times as long as the pitch of the sprocket holes, the resin coating is performed by using 3 nozzles. As a result, the transfer distance of the base film transferred in a single resin coating process is 18 times as long as the pitch of the sprocket holes. It follows that it is possible to set constant the time for the base film to pass through the drying section even if the length LD of the resin film forming region differs.

Abstract: A chip-on-board electronic device includes an electronic device die affixed to a printed circuit board, and electrically interconnected thereto by wirebonds. The electronic device is protected by coating it with a layer of silicon oxynitride and, optionally, an overlying thin layer of a conformal coating such as parylene. Under some circumstances, a protective layer of an organic material may be used instead of the layer of silicon oxynitride. The chip-on-board electronic device may be protected with an overlying layer of the conformal coating.

Abstract: A method for manufacturing a ceramic resonator is disclosed. The method comprises the steps of forming a ceramic piezoelectric device, a capacitor chip and a lead frame, assembling the piezoelectric device and the capacitor chip into the lead frame, and molding the assembled chip by using epoxy resin. A process for making the capacitor includes the steps of cutting a ceramic wafer into a plurality of sub-wafers, printing electrodes on one face of the sub-wafer in a dual-striped form, drying the sub-wafer thus printed, printing another electrode on a central part of another face of the sub-wafer so as to be overlapped with the electrodes of the one face of the sub-wafer, drying the sub-wafer thus printed, baking the sub-wafer thus dried; and cutting the sub-wafer thus baked into a plurality of capacitors.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.

Abstract: A mold for taped lead frame assemblies is provided. The mold has a mold cavity large enough to hold an entire lead frame assembly. A taped lead frame assembly is placed completely in the mold cavity. A cover is used to cover the mold cavity. The cover is spaced apart from the taped lead frame assembly. A riser may be used to provide the spacing between the cover and the taped lead frame assembly, so that the cover does not contact the taped lead frame assembly. An encapsulation material is placed in the mold cavity and then hardened. The encapsulated taped lead frame assembly is then removed from the mold and singulated.

Abstract: A method and device for providing a gate blocking material. Specifically, a method for molding a substrate having known good and bad sites thereon, by blocking the gate area of the bad sites during the molding process. A blocking material or an injection pin are used to interrupt the flow of molding compound through an injection molding system, and thereby prevent molding compound from flowing onto the known bad substrate sites.

Abstract: In an electronic component, an element section is formed on a base, and the element section has functions of at least one of inductance, resistor, and capacitor. Resist film is formed on at least the lateral faces of the base. An unnecessary part of patterned resist film is removed, and a protective member is formed on that removed place. Then remaining resist film is removed. This manufacturing method can provide the electronic component excellent in bonding strength between the protective member and the base.

Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.

Abstract: An air side cover is attached to a proximal end of a housing so as to confine an aerial atmosphere therein. A measured gas side cover is attached to a distal end of the housing so as to confine a measured gas atmosphere therein. A glass sealing material airtightly seals a clearance between an inner surface of an insulator and an outer surface of a sensing element. A contact interface of the glass sealing material protrudes toward a proximal end of the gas sensor compared with at least an adjacent portion of the remainder of the glass sealing material. By melting and hardening a glass pellet, the sensing element is airtightly fixed in the insulator.

Abstract: Techniques for improving the manufacture and structure of leadframe chip scale packages and land grid array packages are described. One aspect of the invention pertains to a method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, wherein a metallic barrier layer and a second metallic layer are utilized as an etching resist. A method, according to another aspect of the invention pertains to covering a metallic barrier layer and second metallic layer with a etch resistant cap such that the etch resistant cap is used as a etching resist. In another aspect of the present invention, a method for treating a conductive leadframe with a CZ treatment is disclosed. In yet another aspect of the present invention, techniques relating to locking grooves within the studs of a studded leadframe are disclosed.

Abstract: A process for the production of a device for measuring or detecting, particularly a probe or a detector, includes the steps of pre-mounting the different active components of the device, of which certain are ultimately gathered in functional subassemblies on and/or in a support body, then potting the pre-mounted resulting assembly, as well as its connection regions with a connection and/or supply cable, to form a substantially monoblock member and, finally, overmolding under pressure the potted member, as well as the proximal portion of the cable, with a thermoplastic material compatible with the resin used, to obtain an apparatus or instrument having the desired shape.

Abstract: A method for producing an electronic component includes placing an enclosed frame on a baseplate. A chip is provided to be fitted within the frame, forming a first given space between the chip and the baseplate and forming a second given space between the chip and the frame. The first given space is enclosed in a hermetically sealed manner by pressing a film onto the chip, except on a surface of the chip facing the baseplate, such that the film surrounds the chip and at least reaches the surface of the baseplate. The second given space is filled with a casting compound. The film is then removed at surface regions of the film being free of the casting compound. Finally, a cover composed of an electrically conductive material is applied on the chip, the casting compound and the frame.

Abstract: A semiconductor chip package having a clip type lead frame and fabrication thereof. The package includes a semiconductor chip having a plurality of bond pads thereon, a first package body having a recess, a plurality of inner leads each connected electrically to a corresponding one of the bond pads, a plurality of outleads each extended from a corresponding one of the inner leads for covering along sides of the first package body, and a second package body which covers the semiconductor chip, a plurality of metallic wires and the inner leads.

Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a set of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the conductors of the component are routed through the lead channels. A set of insertable lead terminals, adapted to cooperate with the specially shaped lead channels, are received and captured within the lead channels, thereby forming an electrical connection between the lead terminals and the conductors of the electronic component(s). A method of fabricating the device is also disclosed.

Abstract: A chip size package is fabricated by: etching portions of a copper film on an insulating film tape, forming a solder mask on the insulating film tape excluding inner holes of metal pattern units and four edge portions of the copper film, electroplating, attaching the semiconductor chip, sealing the semiconductor chip with an epoxy, etching to expose the chip pads, electrically connecting the chip pads by wires, eliminating portions of the copper film remaining at the four edge portions and cutting the insulating film tape into individual units.

Abstract: An encapsulation material for use within a microelectronic device includes a polymeric base resin that is filled with a fibrous reinforcement material. The fiber reinforcement of the encapsulation material provides an enhanced level of crack resistance within a microelectronic device to improve the reliability of the device. In one embodiment, a fiber reinforced encapsulation material is used to fix a microelectronic die within a package core to form a die/core assembly upon which one or more metallization layers can be built. By reducing or eliminating the likelihood of cracks within the encapsulation material of the die/core assembly, the possibility of electrical failure within the microelectronic device (e.g., within the build up metallization layers) is also reduced.

Abstract: The resin system comprises at least two components which can be stored separately and crosslinked with one another at room temperature, preferably without curing accelerators. The first component comprises at least one compound of the formula (I) where A is an unsubstituted or substituted aromatic radical. The second component comprises at least one cyclic anhydride of an organic acid.

Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.

Abstract: Methods for making packages and leadframes are enclosed. The package includes a die, a die pad, leads, bond wires, and an encapsulant. The lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material is applied by molding or liquid encapsulation techniques. The encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described partial etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body. Other surface of the die pad and leads are not covered during the encapsulation step, but rather remain exposed at the lower surface of the package for connecting the package externally.

Abstract: A method of manufacturing a piezoelectric torque transducer is provided, comprising the steps of (a) forming a prepared area on a surface of a torsion member adapted to be strained by an applied torque; (b) providing a piezoelectric element having an axis of maximum strain sensitivity and disposing first and second electrodes on opposite faces of the element, respectively, and attaching an electrical lead to each electrode; (c) connecting electrical leads to the electrodes; and (d) disposing the element on the prepared area and orienting the axis of maximum strain sensitivity on the member and securing the element to the prepared area with a material selected from a group consisting of (i) adhesive material and (ii) potting material.

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.

Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.

Abstract: A resin seal apparatus includes a movable bottom die vertically moved by an elevator mechanism, a transport mechanism horizontally moving the movable bottom die having placed thereon a printed circuit board with a semiconductor chip mounted thereon, an intermediate die abutting against a periphery of the printed circuit board when the movable bottom die is moved upward, a film of resin stretched by a film stretch mechanism over the intermediate die and the printed circuit board, a die for a chip, pressing a back surface of the semiconductor chip via the film of resin, and a top die pressing a top surface of the intermediate die via the film of resin. This apparatus allows a PCB with a semiconductor chip mounted thereon in the form of a flip chip to be sealed with resin in a reduced period of time to fabricate an electronic component.

Abstract: An integrated circuit package which has a flexible circuit that covers an integrated circuit. The flexible circuit contains a conductive line which prevents a probe from accessing the integrated circuit. The conductive line of the flexible circuit can be attached to the power lines, synchronization line, memory erase line, or any other line that will disable, erase or otherwise prevent access to the integrated circuit if the flexible circuit conductive line is broken. The integrated circuit can be mounted to a printed circuit board. The printed circuit board, integrated circuit and flexible circuit can all be enclosed within the package.

Abstract: An epoxy-based soldering flux is used to solder a flip-chip IC device to a metallic bond site on a substrate material. The soldering flux is composed of a thermosetting epoxy resin and a cross-linking agent with inherent flux activity. When heated the cross-linking agent cleans the metal oxides from the metal surfaces on the chip and then reacts with the epoxy resin to form a thermosetting epoxy residue. The flux residue left on the board after soldering does not inhibit the flow of an underfill encapsulant. The underfill binds to the thermosetting residue of the flux which increases adhesion strength preventing delamination of the chip during thermal cycling.

Abstract: An encapsulated integrated circuit is provided including a semiconductor die, a printed circuit board, and an encapsulant. The printed circuit board is conductively coupled to the semiconductor die and comprises a laminate defining first and second major faces. The laminate includes a solder resist layer, an electrically conductive layer, and a bismaleimide triazine resin laminate including a selected laminated layer and an adjacent laminated layer. The electrically conductive layer is interposed between the solder resist layer and the underlying substrate. The selected laminated layer is disposed closer to the first major face than the adjacent laminated layer. The laminate includes at least one void formed therein so as to extend from one of the major faces through the solder resist layer and the electrically conductive layer at least as far as the adjacent laminated layer.

Abstract: An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.

Abstract: In one aspect, the invention includes a method of encapsulating a semiconductor device, comprising: a) providing a semiconductor device; b) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor device; and c) dispensing a liquid encapsulating material through the plurality of orifices and over the semiconductor device. In another aspect, the invention includes a method of forming an electronic package, comprising: a) providing a circuit board having a circuit pattern; b) joining a plurality of semiconductor devices to the circuit board in electrical connection with the circuit pattern; c) providing a dispensing apparatus having a plurality of dispensing orifices proximate the semiconductor devices; d) simultaneously dispensing liquid encapsulating material through at least two of the plurality of orifices and over at least two of the semiconductor devices; and e) curing the liquid encapsulating material.