Abstract: An integrated circuit, including: a first current source; a second current source provided in parallel to the first current source; a first resistor with one end coupled to an output of the first current source; a first bipolar transistor that is diode-connected and is coupled to the other end of the first resistor; a second bipolar transistor that is diode-connected and is coupled to an output of the second current source; a second resistor coupled to the second bipolar transistor; and an output circuit configured to output a voltage based on a first voltage outputted from the first current source and a second voltage outputted from the second current source.

Abstract: A driver circuit includes a first output terminal, a first switch, a second switch, a third switch and a power source. The first output terminal is arranged for outputting a data output. The first switch is selectively coupled between the first output terminal and a power supply node according to a data input. The second switch is selectively coupled between the first output terminal and a first reference node according to the data input. The third switch is selectively coupled between the first reference node and a reference voltage. The power source is configured to selectively provide one of a supply voltage signal and a supply current signal to the power supply node. When the power source is configured to provide the supply voltage signal, the third switch is switched on. When the power source is configured to provide the supply current signal, the third switch is switched off.

Abstract: A bandgap reference (BGR) circuit is provided. The BGR circuit includes a first node, a second node, and a third node. A first resistive element is connected between the second node and the third node. The BGR circuit is operative to provide a reference voltage as an output. The BGR circuit further includes a current shunt path connected between the first node and the third node, the current shunt path being operable to regulate a voltage drop across the first resistive element.

Abstract: A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

Abstract: An adding circuit, device and method for adding M binary operands/numbers. The binary operand (i) of the M binary operands has Ni bits. First, for i=1, . . . , M and j=1, . . . , Ni, the bit (i,j) is applied to a switch (i,j) that might be on if the bit (i,j) is 1, and off if the bit (i,j) is 0. Then a direct current (i,j) is sent through the switch (i,j), the direct current (i,j) having a value of (a) 2j?1 if the switch (i,j) is on, and (b) zero if the switch (i,j) is off. All the direct currents (i,j) with their self-summing capabilities are merged into a combined current on an electrically conductive line. An ammeter on the electrically conductive line displays the decimal value of the sum of the M binary operands.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable pre-charge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a substrate with their drains connected together, but otherwise isolated from each other.

Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

Abstract: A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit. As a regulator voltage reference circuit is enabled via its associated enable signal, an enable precharge signal is also asserted for an initial duration. Each regulator voltage reference circuit includes a voltage setting circuit and a first current limiting transistor in series and operative to interrupt current to the voltage setting circuit when the regulator voltage reference circuit is disabled. A second current limiting transistor is configurably configured as a current mirror with the first current limiting transistor, and a pre-charge bias current from a current source passes through the second transistor.

Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.

Abstract: A sensing device includes a first current mirror configured to mirror a current flowing through a thermistor, a second current mirror configured to mirror a current flowing through a reference resistor a comparator configured to compare voltages on the thermistor and the resistor, and a counter configured to generate a control signal representative of a temperature difference based on the comparison. The control signal controls a mirroring ratio of the second current mirror. The sensing device may be employed to generate a droop current of a voltage regulator.

Abstract: Disclosed are systems, circuits and methods related to controlling of a radio-frequency (RF) power amplifier (PA). In some embodiments, a PA control circuit can include a first circuit configured to generate a replica base current from a base current provided to the PA, with the replica base current being representative of a collector current of the PA scaled by a beta parameter. The PA control circuit can further include a second circuit configured to generate a beta-tracking reference current from a temperature-compensated voltage and a base resistance associated with the PA. The PA control circuit can further include a current steering circuit configured to receive the replica base current and the beta-tracking reference current and generate a proportional current to a clamping node of a base driver. In some embodiments, the replica base current can be obtained by a current-mode comparison of a finger-sensed current with a ramp current.

Abstract: A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.

Abstract: An embodiment of a driving device is proposed for supplying at least one regulated global output current to a load. The driving device includes programming means for programming a value of the global output current within a global current range. Reference means are provided for supplying a reference voltage, which has a value corresponding to the value of the global output current. Conversion means are then used for converting the reference voltage into the global output current. The conversion means may further include a plurality of conversion units for corresponding partial current ranges, which partition the global current range.

Abstract: Techniques are described to mirror currents and subtract currents accurately. In an implementation, a circuit includes a first current source coupled to a first node to provide a current IPD1 and a current mirror coupled to the first node through a first switch T1 to provide a current IREF1. In a closed configuration, the current IREF1 flows from the current mirror into the first node. A sigma delta modulator controls the switch T1 such that over a period of time an average current flowing from the current mirror into the first node is equal to the current IPD1 flowing out of the first node. The sigma delta modulator generates a digital output to control switch T2 to allow a current IREF2 into a second node, thus subtracting a portion of a current IPD2 at the second node over a period of time.

Abstract: In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current generator, and (iii) direct the dependent and constant currents through source and sink current nodes.

Abstract: A current mirror circuit includes an input portion configured to conduct a bias current, and a first current source circuit coupled to the input portion and configured to generate the bias current, and vary the bias current over a range of currents based on a first group of weightings associated therewith. The current mirror circuit also includes an output portion configured to conduct an operational current, wherein the output portion is coupled to the input portion, and a second current source circuit coupled to the output portion and configured to generate the operational current, and vary the operational current over a range of currents based on a second group of weightings associated therewith. The first group of weightings and the second group of weightings are different.

Abstract: In an embodiment, a circuit is disclosed that includes a current mirror including a first transistor pair and a second transistor pair. The first transistor pair includes a first transistor and a second transistor. The second transistor pair includes cascode transistors. The circuit also includes an operational amplifier having an output coupled to both the first transistor and the second transistor.

Abstract: Disclosed is an output stage, and associated apparatus, for a voltage regulator that includes a clamp circuit that is operable to ensure that the output voltage recovers quickly, i.e. that the perturbation of this voltage is limited and remains within a given specification, when entering a standby mode and which is controlled in a supply independent manner.

Abstract: A multiple-input comparator is disclosed. The multiple-input comparator includes a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected to a current source or a current sink. A power inverter utilizing the multiple-input comparator is also disclosed.

Abstract: A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.

Abstract: A circuit exhibiting rectification and amplification characteristics. In particular, a full-wave rectifier, wherein the rectifier has the ability to simultaneously amplify and rectify an input voltage. The circuit comprises transconductor circuit, rectifying circuit and amplifying circuit. The transconductor circuit is adapted for receiving an input voltage from at least one voltage source. The input voltage is then converted into intermediate currents by the transconductor circuit. Thereafter, the rectifying circuit rectifies the intermediate currents current to produce a rectified current. Lastly, the amplification circuit amplifies the input voltage to produce the amplified voltage.

Abstract: A regulator for providing a low dropout voltage at an output node of the regulator is provided. An amplifier has a non-inverting input terminal for receiving an input voltage, an inverting input terminal and an output terminal. A first resistor is coupled between a ground and the inverting input terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. A first transistor is coupled between a voltage source and the second resistor. A current source coupled between the voltage source and a gate of the first transistor provides a bias current. A second transistor coupled between the first transistor and a current mirror has a gate coupled to the output terminal of the amplifier. The first and second transistors are different type MOS transistors. The replica unit generates the low dropout voltage according to a voltage of the output terminal of the amplifier.

Abstract: A supply arrangement, a supply unit and a method in which a switching element is connected in series to an operating voltage and an electrical load, wherein a supply unit supplies an electronic unit with power independently of the switching state of the switching element.

Abstract: In one embodiment, a constant-current generator is connected in series with a dependent (e.g., tail) device. A switched capacitor circuit connected to the gate of the dependent device is operated to (i) charge at least one capacitor of the switched capacitor circuit, (ii) use the at least one charged capacitor to adjust the gate voltage of the dependent device to drive the dependent current through the dependent device to be equal to the constant current through the constant-current generator, and (iii) direct the dependent and constant currents through source and sink current nodes.

Abstract: A direct current generating, management and distribution system includes a first armature winding, a first active rectifier having a first controller and coupled to the first armature winding, a first direct current bus coupled to the first active rectifier, a second armature winding, a second active rectifier having a second controller and coupled to the second armature winding, a second direct current bus coupled to the second active rectifier, a unit controller coupled to the first and second controllers, a first set of switches coupled to the first direct current bus and to the unit controller, a second set of switches coupled to the second direct current bus and to the unit controller, a third switch coupled to the first direct current bus and to the unit controller and a fourth switch coupled to the second direct current bus and the unit controller.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.

Abstract: An apparatus, comprising a load; an output FET having a drain coupled to the load; a first and second of a pair strong FETs, wherein: a) a source of the first of the pair of the strong FETs is coupled to the load; b) a drain of the first pair of the strong FETs is coupled to the source of the second of the of the pair of the strong FETs; the drain of the second pair of the strong FETs is coupled to a gate of the output FET; and a fixed current mirror is coupled to the gate of the first of the pair of the strong FETs.

Abstract: The load driving device disclosed in the specification includes a controller to generate a first control signal based on an input signal, a first output transistor to supply an output current to a load according to the first control signal, a first dividing circuit to output a first divided voltage by dividing a voltage across a first primary electrode and a second primary electrode of the first output transistor by a first transistor and a second transistor connected in serial, a first voltage generating circuit to output a first reference voltage, and a first comparator to supply a first over current detection signal to the controller based on the first reference voltage and the first divided voltage.

Abstract: A step down convertor with a distributed driving system. In one embodiment, an apparatus is disclosed that includes an inductor coupled to an output node. The apparatus also includes first and second circuits. The first circuit can transmit current to the output node via the inductor, and the second can transmit current to the output node via the inductor. The apparatus also includes a third circuit for modifying operational aspects of the first circuit or the second circuit based on a magnitude of current flowing through the inductor.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: An embodiment of a driving device is proposed for supplying at least one regulated global output current to a load. The driving device includes programming means for programming a value of the global output current within a global current range. Reference means are provided for supplying a reference voltage, which has a value corresponding to the value of the global output current. Conversion means are then used for converting the reference voltage into the global output current. In the driving device according to an embodiment of the disclosure, the conversion means include a plurality of conversion units for corresponding partial current ranges, which partition the global current range. Each conversion unit is adapted to convert the reference voltage into a partial output current that contributes to the global output current, with the partial output current that is within the corresponding partial current range.

Abstract: The present invention is related to an output driving device. The output driving device includes: a stabilization unit for generating a correction voltage with a level lower than a power voltage; a first buffer unit for generating a first driving voltage with a swing width; a second buffer unit for generating a second driving signal with a swing width; and an output driving unit for generating an output signal in response to the first and the second driving signals. Accordingly, by supplying a plurality of driving signals with swing widths different from each other corresponding to the characteristics of each output unit respectively, it can set the gate voltage flown into the first output unit not to exceed the breakdown voltage between the gate and the source of the first output unit and can protect the devices of the first output unit as the PMOS transistor.

Abstract: Approximating loci of eigenvalues or characteristic gains of a return ratio matrix of a model of a multi-phase power converter circuit by the loci of the d-d and q-q elements of said synchronous frame of reference applied to said model, allows determination and assessment of stability of the circuit or forbidden operational parameters of the combination of an AC power source and a power converter at an interface thereof by application of a standard Nyquist stability criterion.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: Provided is a voltage regulator in which a maximum output current and a short-circuit output current may be accurately set. As a circuit for determining respective current values of a maximum output current (Im) and a short-circuit output current (Is) of an overcurrent protection circuit, the voltage regulator includes a current mirror circuit for mirroring a current in accordance with an output current so as to be capable of current control, without employing a resistor for converting a current into a voltage. Therefore, the maximum output current (Im) and the short-circuit output current (Is) may be accurately set with respect to an output current (Iout).

Abstract: A power supply voltage detection circuit of the present invention includes a reference signal generation circuit that generates a reference signal according to a power supply voltage, a first transistor having a current flowing between a first terminal and a second terminal, where the current is controlled according to the reference signal, a voltage generation circuit that generates a control voltage according to a potential difference between the power supply voltage and the first terminal of the first transistor, and a second transistor that controls whether or not to output the power supply voltage according to the control voltage. Such circuit configuration enables to accurately detect a low voltage state of the power supply voltage.

Abstract: A current source with low power consumption and reduced on-chip area occupancy. The current source for providing a constant current to a load includes a first circuit that generates a reference current. The first circuit includes a first plurality of interconnected transistors. The current source also includes a characteristic resistor, coupled to the first circuit, that determines value of the reference current. The current source further includes a second circuit and a third circuit. The second circuit, coupled to the first circuit and to the load, generates an output current that is identical to the reference current. The second circuit includes a second plurality of interconnected transistors. The third circuit, coupled to the first circuit, drives a multiple of the reference current into the characteristic resistor. The third circuit includes a third plurality of interconnected transistors.

Abstract: The invention reduces unnecessary electromagnetic radiation noise due to an operation clock signal generated by an oscillator circuit. Random number data outputted by a random number generation circuit is stored in a frequency variable data register. The data stored in the frequency variable data register is replaced by random number data sequentially generated by the random number generation circuit. An oscillator circuit is a circuit generating a clock signal, and the clock signal is supplied as an operation clock signal to an internal circuit through an operation clock signal generation circuit. The frequency of the clock signal from the oscillator circuit is variably controlled in response to the random number data stored in the frequency variable data register. A frequency variable range control register which stores control data for controlling the range of the frequency variably controlled in response to the random number data stored in the frequency variable data register is further provided.

Abstract: The multi-channel power supply comprises a first channel, a second channel, a current sensing module, a current average control circuit, and a modulator. The first channel and the second channel respectively transform an input voltage into an output voltage according to a first pulse width modulation (PWM) signal and a second PWM signal. The current sensing module respectively sense a first channel current and a second channel current to output a first sensing current and a second sensing current. The current average control circuit generates a first error current and a second error current according to the first sensing current and the second sensing current and an average current thereof. The modulator generates the first PWM signal and the second PWM signal according to the first error current, the second error current and the output voltage.

Abstract: An ON/OFF detection circuit for detecting an electronic device includes a switch circuit, a current sampling circuit, an amplifying circuit, and a control circuit. The switch circuit includes an input terminal connected to a constant voltage source, an output terminal coupled to the electronic device, and a control terminal. The current sampling circuit is connected between the input terminal and the output terminal of the switch circuit, and is configured for sampling current flowing to the electronic device and converting sampled current into sampled voltage. The amplifying circuit is configured for filtering and amplifying the sampled voltage. The control circuit controls the ON and OFF of the electronic device and compares the sampled voltages with a comparison voltage to judge the electronic device is qualify or disqualify.

Abstract: This document discusses methods and apparatus for converting an input voltage level to an output voltage level that can be different from the input voltage level. In an example, a converter can include a first switch configured to couple an inductor to a load, a second switch configured to initiate current flow in the inductor, a third switch coupled to a current source, and a controller configured to couple the first switch to the third switch to form a current mirror, to conduct current between the inductor and the load using the first switch, and to control the conducted current using the current source when an output voltage is substantially less than the supply voltage.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: A current injector circuit comprises a clock modulating circuit, a first current injector, a feedback circuit, a first input modulating circuit and a second current injector. The clock modulating circuit receives a clock, a control signal, and an output. The first current injector has an input coupled to the clock modulating circuit, and an output coupled to a power supply terminal for providing a first current. The feedback circuit is coupled between the power supply terminal and another input of the clock modulating circuit. The feedback circuit is for providing the control signal for controlling the clock modulating circuit. The first current injector provides the first current in response to the clock modulating circuit. The first input modulating circuit receives an input signal, the control signal, and an output. The second current injector has an input coupled to the first input modulating circuit, and an output for providing a second current.

Abstract: A delay method for determining an activation moment of an output device in a circuit system is disclosed. The delay method includes determining resistance of an over-current flag pull-high resistor of the circuit system, generating a current according to the resistance of the over-current flag pull-high resistor and a voltage drop across the resistor, duplicating the current to generate a first mirror current, delaying an enable signal of the circuit system according to the first mirror current to generate a charging activation signal, providing a charging current according to the charging activation signal, and determining the activation moment of the output device according to the activation current.

Abstract: One aspect is a circuit arrangement having a load current path with a load transistor having a first and a second load path terminal and a control terminal. A first measurement current path includes a measuring transistor having a first and a second load path terminal and a control terminal. The control terminals and first load path terminals of the load transistor and the measuring transistor are coupled. A first regulating circuit has a controllable resistor and is designed to drive the resistor depending on electrical potentials at the second load path terminals of the load transistor and of the measuring transistor. A current mirror circuit is coupled between the first measurement current path and a second measurement current path. A deactivation circuit is designed to deactivate the first regulating circuit depending on a current flowing through the measuring transistor.

Abstract: A two-terminal current controller regulates a first current flowing through a load, which is coupled in parallel with the two-terminal current controller, according to a voltage established across the two-terminal current controller. When the voltage established across the two-terminal current controller does not exceed a first voltage, the two-terminal current controller conducts a second current related to a rectified AC voltage, thereby limiting the first current to zero and regulating the second current according to the load voltage. When the voltage established across the two-terminal current controller is between the first voltage and a second voltage, the two-terminal current controller conducts the second current, thereby limiting the first current to zero and limiting the second current to a constant value larger than zero. When the voltage established across the two-terminal current controller is greater than second voltage, the two-terminal current controller is turned off.

Abstract: High-accuracy overcurrent detection is performed, while a loss resulting from the current detection is significantly reduced. A switch section outputs the voltage between the both terminals of a current detection resistor using an AND signal between an output signal from a hysteresis comparator and an output signal from a pre-driver. The voltage is filtered by an electrostatic capacitor element and a resistor, and inputted to a comparator. The comparator makes a comparison between the signals inputted to the two input terminals thereof, and outputs the result of the comparison to a digital filter. When an overcurrent begins to flow in a power supply unit, the levels of the voltages inputted to the two input terminals of the comparator are inverted so that the comparator outputs an inversion signal to the digital filter. The digital filter outputs a detection signal to an overcurrent detection circuit when an arbitrary time has elapsed.