Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.

Abstract: Provided is a an electronic system (1) comprising a plurality of sub blocks (21, 22, . . . ), a differential amplifier (3), a voltage regulation loop comprising a first transistor (40) and a variable resistor (5), and a plurality of additional transistors (41, 42, . . . ). The input reference voltage (VRF) and the variable resistor are configured such that a first sub block (21) is supplied with its required power supply output voltage (VDD1) by the transistor to which it is connected. The amplifier is configured to output on each of its outputs a power supply reference voltage (VG1, VG2 . . . ) such that each sub block (22, . . . ) other than the first sub block is supplied with its required power supply output voltage (VDD2 . . . ) by the transistor to which it is connected.

Abstract: A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.

Abstract: A method includes: providing a modulation circuit, determined an operation mode of a memory array, providing a first voltage corresponding to a positive temperature coefficient in response to a read operation of the memory array, and providing a second voltage corresponding to a negative temperature coefficient in response to a write operation of the memory array. The modulation circuit is configured to generate a temperature-dependent voltage and provide the same to the memory array.

Abstract: A supply voltage sensitivity of an output current of a bias current generator circuit is reduced. The bias current generator includes a plurality of transistors and a plurality of resistors coupled to the plurality of transistors. The supply voltage sensitivity of the output current of the bias current generator circuit is reduced by applying a second bias current generated by the bias current generator circuit to a first bias current generated by the bias current generator circuit.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

Abstract: A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Abstract: A current detection circuit includes normally-on-type and a first normally-off-type switching elements with main current paths that are connected in series, and a second normally-off-type switching element that has a source and a gate that are connected to a source and a gate of the first normally-off-type switching element and a drain that is connected to a constant current source, and executes a division process by using drain voltages of the two normally-off-type switching elements.

Abstract: A power generation device includes a band gap reference (BGR) circuit configured to generate a reference voltage independent of an environmental change, and a voltage generation circuit configured to transfer an input power voltage based on a sum of the reference voltage and an internal ground voltage to generate an internal power voltage.

Abstract: A voltage differential testing circuit can include a first positive line configured to connect to a positive voltage source, and a first negative line configured to connect to a negative voltage source. The circuit can include a plurality of components arranged and configured to output an output voltage when a voltage differential between a positive voltage line and a negative voltage line is within a voltage range.

Abstract: Systems and/or devices for efficient and intuitive methods for implementing artificial neural networks specifically designed for parallel AI processing are provided herein. In various implementations, the disclosed systems, devices, and methods complement or replace conventional systems, devices, and methods for parallel neural processing that (a) greatly reduce neural processing time necessary to process more complex problem sets; (b) implement neuroplasticity necessary for self-learning; and (c) introduce the concept and application of implicit memory, in addition to explicit memory, necessary to imbue an element of intuition. With these properties, implementations of the disclosed invention make it possible to emulate human consciousness or awareness.

Abstract: A voltage reference circuit that can operate in a large supply voltage range with high PSRR, that dissipates low-power for a given output noise, and that has a low temperature-coefficient (TC) across a wide-temperature range. The voltage reference circuit does not require any calibration for low TC and high PSRR, occupies a relatively small circuit area, may be used without additional supply filtering in noisy or high-ripple supply environments, and is more robust against device mismatch effects particularly compared to designs based on sub-threshold operations. The voltage reference circuit is a special form of constant transconductance circuit that uses current mirror ratios that are chosen to achieve high PSSR and low noise properties. The device saturation voltage may be chosen so that flat temperature characteristics may be achieved.

Abstract: A semiconductor device in which the accuracy of arithmetic operation is increased by correction of the threshold voltage of a transistor can be provided. The semiconductor device includes first and second current supply circuits, and the second current supply circuit has the same configuration as the first current supply circuit. The first current supply circuit includes first and second transistors, a first capacitor, and first to third nodes. A first terminal of the first transistor is electrically connected to the first node, and a back gate of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the first capacitor. A gate of the first transistor is electrically connected to the second node, and a second terminal of the first capacitor is electrically connected to a second terminal of the first transistor.

Abstract: An electronic circuit for voltage regulation is disclosed, the circuit generally includes a low-dropout (LDO) voltage regulator function block, including a primary feedback loop, and an output voltage stabilizer block connected to the LDO voltage regulator function block outside the primary feedback loop, wherein the output voltage stabilizer block includes a plurality of peak voltage suppression circuits and a plurality of dip voltage suppression circuits. In some embodiments, the output voltage stabilizer block is set at low bias current to minimize current consumption at normal condition. Other useful features and advantages of an electronic circuit for voltage regulation are disclosed.

Abstract: A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.

Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.

Abstract: Disclosed is a reference voltage generating circuit including a bandgap reference voltage generating circuit, a voltage controlled current source circuit, a current mirror circuit, an input voltage generating circuit, and a voltage controlled voltage source circuit. The bandgap reference voltage generating circuit generates a bandgap reference voltage. The voltage controlled current source circuit generates a reference current according to the bandgap reference voltage. The current mirror circuit generates a mirrored current according to the reference current. The input voltage generating circuit determines an input voltage according to the mirrored current. The voltage controlled voltage source circuit generates a reference voltage according to the input voltage.

Abstract: A noise suppression circuit includes a resistor-capacitor (RC) filter where a resistive element of the RC filter has a first terminal configured to receive an input data stream and a second terminal coupled to a circuit node Vrc and a capacitive element coupled to the circuit node, a logic gate having an input coupled to the circuit node and an output configured to provide a filtered data stream, and a switch. The switch is configured to short out the resistive element of the RC filter when the input data stream and the filtered data stream are at a same value and not short out the resistive element when the input data stream and the filtered data stream are at different values.

Abstract: A current detection circuit includes an N-type first transistor configured to supply a first current to an output terminal, an N-type second transistor that constitutes a current mirror circuit with the first transistor, a comparison circuit configured to output a detection result showing whether or not the first current is larger than a predetermined threshold based on a current flowing through the second transistor, a ground fault detection circuit configured to output a result detecting a ground fault of the output terminal, and a logical circuit configured to output a current detection signal showing whether or not the first current is an overcurrent based on the detection result of the comparison circuit and the ground fault detection result of the ground fault detection circuit.

Abstract: A current measurement circuit may use a probabilistic technique to determine a current from a circuit block. In one embodiment, the circuit includes a comparator circuit, a first current sensing element (such as a first resistor), and a control circuit. The first current sensing element is coupled to the comparator circuit to establish a first comparator input signal representative of the current at an input of the comparator circuit. The control circuit is coupled to the comparator circuit to obtain a first plurality of comparator output decisions corresponding to the first current sensing element for a specified count, determine a first proportion of comparator output decisions meeting a specified criterion, and determine a voltage value of the first comparator input signal from the first proportion. The control circuit is configured to determine a current value using the voltage value of the first comparator input signal and an impedance value of the first current sensing element.

Abstract: Systems and/or devices for efficient and intuitive methods for implementing artificial neural networks specifically designed for parallel AI processing are provided herein. In various implementations, the disclosed systems, devices, and methods complement or replace conventional systems, devices, and methods for parallel neural processing that (a) greatly reduce neural processing time necessary to process more complex problem sets; (b) implement neuroplasticity necessary for self-learning; and (c) introduce the concept and application of implicit memory, in addition to explicit memory, necessary to imbue an element of intuition. With these properties, implementations of the disclosed invention make it possible to emulate human consciousness or awareness.

Abstract: A semiconductor device is provided and includes: a voltage sensing circuit configured to output first and second sensing voltages based on a target voltage applied thereto; and a comparing circuit configured to generate a monitoring output signal based on levels of the first and second sensing voltages, wherein the voltage sensing circuit includes: a first transistor including a gate to receive a reference bias voltage, a source connected to an input node, and a drain connected to one end of a first resistive element; a second transistor provided in a current mirror structure with the first transistor, and including a drain connected to a third resistive element; and a second resistive element connected to another end of the first resistive element, the first sensing voltage being provided to both ends of the second resistive element, and the second sensing voltage being provided to both ends of the third resistive element.

Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror.

Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.

Abstract: A linear regulator with indirect leakage compensation is presented. The regulator has a pass device coupled between an input voltage and an output node, a feedback loop for controlling the pass device based on a reference voltage and a feedback voltage that depends on an output voltage, an off-state device that is kept in the off-state, and a leakage compensation circuit for sinking a leakage compensation current from the output node, in dependence on a leakage current of the off-state device. The off-state device is coupled between the leakage compensation circuit and an intermediate voltage level of the linear regulator. The intermediate voltage level is a voltage level between the input voltage level and ground, with a magnitude of the intermediate voltage level being smaller than a magnitude of the input voltage level. A corresponding method of operating a linear regulator with leakage compensation is presented.

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.

Abstract: A voltage generator circuitry includes first to third bipolar transistors having commonly-connected base electrodes, first and second current mirror circuitries, first and second differential amplifiers; a first resistor; and a current-voltage conversion circuitry. The first current mirror circuitry supplies currents to the first to third bipolar transistors and to the current-voltage conversion circuitry. The second current mirror circuitry supplies currents to the first to third bipolar transistors, and s to the current-voltage conversion circuitry. The first and second differential amplifiers control the first and second current mirror. The current-voltage conversion circuitry converts a sum current of the first and second currents into an output voltage.

Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.

Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.

Abstract: A voltage-current conversion circuit includes a voltage-current conversion resistor connected to an input terminal, and a current mirror circuit which mirrors a current supplied from the voltage-current conversion resistor, wherein the current mirror circuit is constructed to include a depletion-type transistor whose source voltage is biased to be higher than the substrate voltage.

Abstract: An enhancement mode GaN FET based gate driver circuit including an active pre-driver to drive a high-slew rate, high current output stage GaN FET. Due to the active driver current from the pre-driver, the output stage pull-up FET can turn on faster as compared to a pre-driver that utilizes a passive pull-up load. The active pre-driver must provide a voltage to drive the gate of the output stage pull-up FET which is higher than the normal supply voltage to enable the maximum output level of the driver FET to approach the normal supply voltage. A feedback circuit is included in the active pre-driver to avoid the need for two supply voltages.

Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference formed by a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.

Abstract: A power supply control apparatus controls power supply via a semiconductor switch, by a driving circuit turning ON or OFF the semiconductor switch. A current circuit pulls in a current from the drain of the semiconductor switch via a resistance. The current value Ic of the current that is pulled in by the current circuit fluctuates in the same direction as a fluctuation direction of the ON resistance value of the semiconductor switch, depending on the ambient temperature of the semiconductor switch. If the source voltage of the semiconductor switch is lower than a voltage at the other end of the resistance, the driving circuit turns OFF the semiconductor switch.

Abstract: A charge pump circuit generates a charge pump voltage that powers a bias circuit. The bias circuit generates a reference current and generates switch currents from the reference current. Gate-source voltages are generated from the switch currents and applied to switching components of switch circuits to connect two nodes. The gate-source voltages can be generated in the bias circuit and provided to the switch circuits. The gate-source voltages can also be generated in the switch circuits.

Abstract: A method and apparatus for operating a semiconductor light source is presented. In particular there is a current regulator for regulating a current flowing through a light emitting diode device. The current regulator includes a first switch for receiving a first current flowing through the semiconductor light source and a control circuit coupled to the first switch and adapted to provide a second current proportional to the first current. The current regulator is adapted to regulate the first current using the second current.

Abstract: The analog switch includes: a clock generation circuit configured to generate a first clock and a second clock; a transfer circuit including an NMOS transistor having a source and a back gate connected to each other, and a PMOS transistor having a source and a back gate connected to each other, one of which has a drain connected to the source of the other, and a source connected to a signal input terminal, and the other of which has a drain connected to a signal output terminal; a first control signal generation circuit configured to generate a control signal for switching the PMOS transistor based on a voltage at the signal input terminal and the first clock; and a second control signal generation circuit configured to generate a control signal for switching the NMOS transistor based on the voltage at the signal input terminal and the second clock.

Abstract: The constant current circuit includes a constant current generation circuit, a start-up detection circuit configured to detect start-up of the constant current generation circuit, and a clamp circuit configured to output a start-up voltage to the constant current generation circuit. The start-up voltage output from the clamp circuit is a voltage close to gate voltages that are higher than gate voltages of transistors that form a current mirror circuit of the constant current generation circuit, in a state where the constant current generation circuit is operating.

Abstract: A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

Abstract: A voltage generator includes a bias voltage generation circuit and a compensation circuit. The bias voltage generation circuit generates a first bias voltage based on a reference current and generates a second bias voltage based on the first bias voltage. The compensation circuit changes a voltage level of the first bias voltage based on the second bias voltage.

Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.

Abstract: A pixel circuit for a display device operable in an initialization phase, a compensation phase, a data programming phase, and an emission phase, whereby the one horizontal time is minimized while maintaining accurate compensation of the threshold voltages of the drive transistors, and further accounting for any variations in the voltage supplies. The pixel circuit includes a first drive transistor configured to control an amount of current to a light-emitting device during an emission phase depending upon voltages applied to a gate and a first terminal of the first drive transistor; and a second drive transistor that is configured as a source follower, wherein a first terminal of the second drive transistor is connected to a first power supply line and a second terminal of the second drive transistor is connected to a first terminal of the first drive transistor. The first drive transistor is one of a p-type or n-type transistor and the second drive transistor is the other of a p-type or n-type transistor.

Abstract: A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (IIN) and generate a mirrored current (IM), where IM=K*IIN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1?m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.

Abstract: Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide first, second, and third bias signals, respectively. The example apparatus further includes a voltage output circuit configured to receive the first, second, and third bias signals. The voltage output circuit includes an output circuit and a current circuit. The output circuit includes an output node, a first node, and an input circuit configured to receive the first bias signal. The output circuit is configured to provide an output voltage at the output node having a magnitude based on the magnitude of the first bias signal. The current circuit includes a first transistor configured to receive the second bias signal and further includes a second transistor configured to receive the third bias signal. The first transistor and second transistor are coupled in parallel and to the first node.

Abstract: A PVT-independent fixed delay circuit includes a circuit structure that has a current generator and a multi-level inverter-based time delay unit. The inverter-based time delay unit has at least two NMOS transistors M5, M6, and at least two PMOS transistors M7, M8. The current generator has a circuit structure including at least two NMOS transistors M1, M2, at least two PMOS transistors M3, M4 and a resistor RS.

Abstract: A digital input circuit adopts a first state when an input signal is below a lower threshold value and adopts a second state when the input signal is above an upper threshold value. The digital input circuit comprises first and second subcircuits that exhibit a non-ideal current output behavior at least in the second state, and each comprises a current stabilizing element with a driving circuit and a voltage stabilizing element. The first and second subcircuits are configured such that, at least in a portion of the second state, an electric current flowing through the first subcircuit's voltage stabilizing element consists substantially of a stabilized current of the second subcircuit, and an electric current that flows through the second subcircuit's voltage stabilizing element consists substantially of a stabilized current of the first subcircuit, such that the non-ideal current output behavior of the first and second subcircuits compensate for each other.

Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.

Abstract: Multiple sensors are coupled to a first pin of a PSI5 transceiver to receive a sensor bus signal. A Manchester decoder is coupled to a second pin and a battery is coupled to a third pin. A comparator receives a first voltage that is proportional to a current on the sensor bus signal and a second voltage that is proportional to a base current on the sensor bus signal and sends a data output signal to the second pin. A sample-and-hold circuit captures a third voltage used to effect the second voltage responsive to a high value on a base current sampling signal. A base-current-renewal circuit detects edge transitions on the data output signal and when the data output signal has no edge transitions for a period of time greater than a gap time defined in a PSI5 standard, sets the base current sampling signal high.

Abstract: A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.