Abstract: According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360° signal and on the 180° signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Abstract: A test apparatus for testing a device under test includes a first timing comparator obtaining a device output signal output from the device under test at a timing designated by a first strobe signal, a second timing comparator obtaining the device output signal at a timing designated by a second strobe signal supplied later than the first strobe signal, a preceding edge judging circuit, when rising and falling signals are input at the same timing as the device output signal, judging which one of the rising and falling signals arrives at the first and second timing comparators at an earlier timing, a preceding edge detecting circuit adjusting a timing at which the first strobe signal is supplied so that the first timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive earlier, and a following edge detecting circuit adjusting a timing at which the second strobe signal is supplied so that the second timing comparator obtains, at a timing

Abstract: A high frequency delay circuit operable to output a high frequency signal delayed for a desired delay time. The high frequency delay circuit includes: a variable delay circuit operable to receive a reference signal of which a frequency is lower than the high frequency signal, and to output a delay reference signal delayed from the reference signal for the desired delay time in advance; and a multiplier operable to generate the high frequency signal, of which a frequency is a frequency of the delay reference signal multiplied by a predetermined value, and to output the generated high frequency signal at timing according to a phase of the delay reference signal.

Abstract: A system for estimating a length of a conductor (110) having a first end (111) and a second end (112) includes a device (120) capable of placing an electric signal on the conductor, an impedance element (130) that maintains the electric signal within a predetermined voltage range, and a timer (140). The device places the electric signal on the conductor such that the electric signal travels along the conductor from the first end to the second end and back to the first end. The timer determines a time required for the electric signal to travel along the conductor from the first end to the second end and back to the first end. The length of the conductor may be estimated based on the time. A compensation factor may be determined based on the length or the time, and may be used to compensate for signal attenuation in the conductor.

Abstract: A time of an event can be determined by acquiring an amplitude, at the time of the event, of at least two periodic timing signals that are out of phase with each other. The time of the event within a cycle of at least one of the timing signals can be determined as a function of the amplitudes of the timing signals. The phase angle and complex coordinates of at least one of the timing signals can be determined as a function of the amplitudes. The time of the event within a cycle of a timing signal can be determined as a function of the phase angle or complex coordinates of the timing signal at the time of the event.

Abstract: There is provided an electric circuit that outputs a timing signal and a recovered clock.

Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing compara

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A method for analyzing length differences in differential signal paths includes: loading a design file of the differential signal paths from a storage device (9); simulating the differential signal paths based on the design file; dividing simulated differential signal paths into a plurality of segments by impedance division positions that show impedance discontinuity; predefining an acceptable length difference limit for each divided segment, and calculating an real length difference for each divided segment; comparing the real length difference with the acceptable length difference limit correspondingly to generate a plurality of analyzed results corresponding to the plurality of divided segments; selecting one or more compared segments to check analyzed results of selected segments; and locating the selected segments in the simulated differential signal paths, and generating analyzed information comprising analyzed results of the selected segments. A related system is also disclosed.

Abstract: A method and apparatus for measuring or converting voltage, the method comprising: applying an input voltage to a primary delay line; applying a reference voltage to a timer delay line; propagating a delay signal through the primary delay line; propagating a timer signal through the timer delay line; establishing a sampling period based on the timer signal propagation; and measuring an extent of delay signal propagation along the primary delay line during the established sampling period, the measured signal propagation extent being indicative of a difference between the input voltage and the reference voltage.

Abstract: A high-sensitivity measuring instrument comprising at least two sensors for detecting the same characteristics by touching a substance being measured with a specified time difference, wherein the between detection signals taken out simultaneously from respective sensors is determined, the difference between characteristic values upon elapsing the specified time difference is determined from the difference between detection signals, a reference time of measurement and a reference characteristic value at that time are preset, a time axis having a time pitch of a specified time difference is set, and a measurement value is obtained at a point in time elapsing an arbitrary time pitch from the reference time. Objective measurement characteristics can be detected by the measuring instrument not in the form of difference or variation but as an absolute value with high accuracy and sensitivity.

Abstract: A method of determining the critical path of a circuit includes first determining the paths, their mean path transit times and their path transit time fluctuations. Paths having similar statistical parameters are combined to form one path group. For each path group, a statistical group figure is, then, calculated and, for the totality of paths considered, a statistical total figure is calculated. Finally, the critical paths of the circuit are determined by taking into consideration the total figure, comparing the group figures at or above a critical path transit time Tc.

Abstract: The invention concerns a method and a device for phase calculation from attenuation values using a Hilbert transform for reflectometric measurements in the frequency domain. The invention is characterized in that the measuring system comprises a signal source for a measurement signal, a coupling element connected to the signal source, and an object to be measured connected to the coupling element. The part of the measurement signal reflected by the object to be measured is uncoupled via the coupling element and measured at a collector. The invention is further characterized in that an attenuator is mounted in the signal path, between the coupling element and the object to be measured. The attenuator can also be comprised in the coupling element.

Abstract: A system and method compensate for phase noise of a spectrum analyzer based on an established model of the phase noise that accommodates a variety of operating states of the spectrum analyzer. The model is used to form an array that is applied to extract an output signal from measurement traces that are acquired by the spectrum analyzer.

Abstract: A method compensates for phase differences between sampled values of first and second AC waveforms. The method employs a phase angle compensation factor and sequentially samples a plurality of values of each of the waveforms. For a positive compensation factor, second sampled values are adjusted to correspond with first sampled values by employing, for a corresponding second sampled value, a preceding second sampled value plus the product of: (i) the compensation factor and (ii) the difference between the corresponding second sampled value and the preceding second sampled value. Alternatively, for a negative compensation factor, the second sampled values are adjusted by employing, for the corresponding second sampled value, the preceding second sampled value minus the product of: (i) the sum of one plus the compensation factor and (ii) the difference between the preceding second sampled value and the second sampled value preceding the preceding second sampled value.

Abstract: A method of characterizing a circuit comprises the steps of measuring a first delay associated with the circuit when the circuit is substantially unloaded; measuring a second delay associated with the circuit when the circuit is loaded by a predetermined impedance; determining a difference between the second delay and the first delay, the delay difference corresponding to a switching impedance associated with the circuit; and determining a characterization parameter of the circuit, the characterization parameter being a function of at least the switching impedance associated with the circuit. The methodologies of the present invention are directed primarily to individually evaluating pullup and pulldown delays with substantial precision (e.g., sub-picosecond) for a representative set of circuits in the presence of an arbitrary switching history.

Abstract: A method is contemplated. According to the method, capacitances in a first resistance/capacitance (RC) extraction corresponding to a circuit are modified. Each capacitance is modified to estimate Miller effect on that capacitance. A ratio of a total capacitance on a first wire after the modification in the first RC extraction to a total capacitance on the first wire before the modification in the first RC extraction is calculated. Capacitances in a second RC extraction that are coupled to the first wire are modified according to the ratio. The second RC extraction is a reduced extraction as compared to the first RC extraction. A timing analysis is performed for the circuit using the second RC extraction with capacitances modified to estimate Miller effect.

Abstract: A method and a circuit for detecting variations of at least one environmental parameter of an integrated circuit, including evaluating a propagation delay of an edge in delay elements sensitive to variations of the environmental parameter, and comparing the present or measured delay with at least one reference value.

Abstract: Disclosed is a method of measuring the time signal of an electronic device including steps for measuring a true signal and an inverted signal. The measured true path signal and inverted path signal are combined to reduce measurement error and provide an accurate measurement of the time signal of the device under test. Also disclosed is an interface for use between a device-under-test and test equipment. The interface includes means for alternately switching a time signal from the device-under-test to provide a true signal path and an inverted signal path for measurement. A system embodiment of the invention is also disclosed in which an interface and measuring means are used to alternately measure and combine a true signal and an inverted signal to provide an accurate time measurement result.

Abstract: Phase noise is at least partially cancelled for an interferometric system by using a delay/phase cross-correlation approach for two interferometers within the system. The cross-correlation approach may be used in measuring group delay of a device under test and includes determining the differences between the phase of the output of each interferometer at time t and the phase of the same output at the time t minus the delay of the other interferometer. In one embodiment, the first phase difference is the difference between the phase of a test interferometer output at time t and the phase of the test interferometer output at the time t offset by the known delay of a reference interferometer. The second phase difference is calculated using the same technique, but the time offset is a delay representative of the relative delay of two light propagations within the test interferometer.

Abstract: Propagation time Tp of an ultrasound signal between two spaced-apart transducers constituting an emitter and a receiver is measured. The emitter transducer is subjected to an excitation signal of n successive pulses of period Te giving rise to an ultrasound signal being emitted towards the receiver transducer which receives the ultrasound signal generating and outputting a receive signal. A measurement of an intermediate propagation time Tint is started when the emitter transducer begins to be excited. The receive signal is detected and the oscillations in the receive signal are counted. Measurement of the intermediate propagation time Tint is stopped when an ith oscillation is detected. The propagation time Tp is determined by taking the difference Tint?i×Te. Advantageously, measurement of Tint is stopped for an ith oscillation of the receive signal that corresponds to the receive signal being at a maximum amplitude.

Abstract: A propagation delay time measuring method of measuring a propagation delay time of a test signal propagating along one of a first signal path serially connecting to the first signal path through which a semiconductor testing apparatus includes a driver and a comparator electrically connected to a device under test.

Abstract: A method and system for determining and compensating for phase and time errors in an optical receiver. The method and system includes use of a measurement and reference signal; deriving phase and time errors; and providing compensation values to the optical receiver. The operating frequency and/or other operating parameters associated with phase and time errors are determined and recorded to allow for proper compensation to the optical receiver.

Abstract: A timing generator includes a reference signal generating unit for generating a reference signal of a predetermined frequency, a variable delay circuit unit for outputting the timing signal which results from delaying the reference signal by a predetermined time, and a delay amount measuring unit for measuring a delay amount of the variable delay circuit unit, whereby the timing generator controls the delay amount of the variable delay circuit unit based on the delay amount measured by the delay amount measuring unit. Since the frequency of the reference signal is continuously modulated within a very small frequency range, the delay amount measuring unit can measure the delay amount of the variable delay circuit unit highly accurately. In addition, since the delay amount of the variable delay circuit unit can be controlled on the basis of the measured delay amount, it is possible to generate the accurately delayed timing signal.

Abstract: A phase delay characteristic measuring apparatus includes an in-phase component calculating means for outputting a correlation value between input sampling data of the input signal and the output signal and ideal sine waveform data as a baseband I signal (in-phase component), a quadrature component calculating means for outputting a correlation value between the input sampling data of the input signal and the output signal and ideal cosine waveform data as a baseband Q signal (quadrature component), a phase angle calculating means for outputting phase angles of the input signal and the output signal based on the baseband I signal and the baseband Q signal, and a phase delay calculating means for calculating an amount of phase delay of the tested device from the phase angles of the input signal and the output signal.

Abstract: A method is contemplated. According to the method, capacitances in a first resistance/capacitance (RC) extraction corresponding to a circuit are modified. Each capacitance is modified to estimate Miller effect on that capacitance. A ratio of a total capacitance on a first wire after the modification in the first RC extraction to a total capacitance on the first wire before the modification in the first RC extraction is calculated. Capacitances in a second RC extraction that are coupled to the first wire are modified according to the ratio. The second RC extraction is a reduced extraction as compared to the first RC extraction. A timing analysis is performed for the circuit using the second RC extraction with capacitances modified to estimate Miller effect.

Abstract: A technique for deskewing digitizer channels in an automatic test system includes applying a waveform of known frequency to the input of each digitizer channel. Each digitizer channel samples the waveform to produce a respective data record. A Discrete Fourier Transform (DFT), or a portion thereof, is then taken for each data record to determine, at minimum, the phase of the waveform. Phase differences across different digitizer channels are converted to time differences, which values are applied to subsequent digitizer measurements to correct for timing skew. Because a large number of samples in a digitizer's data record contribute to the computed phase of the waveform, the effects of timing jitter are substantially eliminated from skew measurements, without the need for repeating measurements and explicitly averaging results.

Abstract: A propagation delay time measuring method of measuring a propagation delay time of a test signal propagating along one of a first signal path and a second signal path serially connecting to the first signal path through which a semiconductor testing apparatus includes a driver and a comparator electrically connected to a device under test, the method includes: a first connecting step of connecting an end of the first path to the driver and the comparator; a first output step of outputting a test signal from the driver to the first path; a first reflect signal receiving step of receiving a test signal at the comparator, defined as a first reflect signal, reflected at another end of the first path; a first timing detecting step of detecting a timing, defined as a first timing; a second connecting step of connecting an end of the second path to another end of the first path; a second output step of outputting the test signal from the driver to the second path; a second reflect signal receiving step of receiving

Abstract: A preferred integrated circuit (IC) includes a first pad electrically communicating with at least a portion of the IC. The first pad includes a first driver and a first receiver, with the first driver being configured to provide a first pad output signal to a component external to the IC, and the first receiver being configured to receive a first pad input signal from a component external to the IC. The first receiver also is configured to provide, to a component internal to the IC, a first receiver digital output signal in response to the first pad input signal. A first test circuit also is provided that is internal to the IC. The first test circuit is adapted to provide information corresponding to the driver clock-to-q time of the first pad. Systems, methods and computer-readable media also are provided.

Abstract: A sensor for measuring the dielectric constant of a fluid uses time of flight measurements. The sensor has a conduit for the fluid, preferably a transmission line. The dielectric constant of the fluid affects tranmission of electrical energy along the transmission line. An electrical generator, having as output an electrical transient, is operably connected to one end of the transmission line for transmitting the electrical transient along the conduit, where propagation of the electrical conduit is affected by the fluid. A receiver is connected to the other end of the conduit for detecting electrical transients that have passed along the conduit from the electrical generator.

Abstract: A digital protective relay system is capable of making sampling timing the same among plural protective relay device which operate independent from each other by using a signal from a GPS satellite. The sampling timing is made the same regardless of the time lag from which it is sent downstream with the concomitant transmission delay time in the case of data communications, or regardless of the time lag from which it is sent upstream.

Abstract: An apparatus and method for deskewing single-ended signals from different driver circuits of an automatic test system provides enough of a reduction in skew to allow differential signals to cross at or near their 50%-points. In accordance with this technique, first and second driver circuits are respectively coupled to first and second inputs of a measurement circuit through pathways having known and preferably equal propagation delays. The first and second driver circuits each generate an edge that propagates toward the DUT, and reflects back when it reaches a respective unmatched load at the location of the DUT. In response to the edge and its reflection, the first and second inputs of the measurement circuit each see a first voltage step and a second voltage step. The interval between the first and second voltage steps is then measured for each input of the measurement circuit.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: A method and a circuit for detecting variations of at least one environmental parameter of an integrated circuit, including evaluating a propagation delay of an edge in delay elements sensitive to variations of the environmental parameter, and comparing the present or measured delay with at least one reference value.

Abstract: A testing apparatus and method which can easily measure and evaluate, on a tester, transistor characteristics of a wafer of the same lot or wafer, and can measure high-speed operation timing in a high precision.

Abstract: A time measuring device includes: an input signal detecting unit for detecting three or more edges in an input signal and to output three or more detection signals in parallel, the three or more detection signals changing based on the three or more edges, respectively; a converting unit for converting phase differences between change timings of the detection signals and clock edges in a reference clock having a predetermined operating frequency into analog voltage values, respectively; a counting unit for counting, from change timings of at least two of the detection signals, number of the clock edges between the clock edges from which at least two detection signals are respectively delayed by the phase differences corresponding to at least two detection signals; an operating unit for calculating a time interval between edges of the three or more edges based on the analog voltage values and the number of clock edges.

Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the test clock signal in the test mode.

Abstract: A phase delay characteristic measuring apparatus includes an in-phase component calculating means for outputting a correlation value between input sampling data of the input signal and the output signal and ideal sine waveform data as a baseband I signal (in-phase component), a quadrature component calculating means for outputting a correlation value between the input sampling data of the input signal and the output signal and ideal cosine waveform data as a baseband Q signal (quadrature component), a phase angle calculating means for outputting phase angles of the input signal and the output signal based on the baseband I signal and the baseband Q signal, and a phase delay calculating means for calculating an amount of phase delay of the tested device from the phase angles of the input signal and the output signal.

Abstract: LED lamp circuitry that emulates an incandescent lamp's behaviour upon remote verification of the LED lamp. The invention presents a fuse blow-out circuit and a cold filament detection circuit permitting the use of LED lamps in applications, such as railway signal light applications, where there is a need for remote monitoring of the lamps, while keeping the advantageous features of lower power consumption and longer life. The invention also provides a control circuit for enabling/disabling the power supply to LED lamps in relation to the level of the line voltage. The advantage of this embodiment is to avoid unwanted functioning of the LED lamp caused by interference from surrounding electrical cables.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: Absolute delay of a FTD is characterized by applying a stimulus signal to a first port of the FTD. A second port of the FTD is coupled to a delay element having a known delay and a reflective termination. A drive signal is applied to a third port of the FTD. A time domain reflection response to the stimulus signal is obtained and a signal peak within the response that corresponds to a return signal from the reflective termination is identified. Absolute delay of the frequency translation device is then extracted based on the known delay of the delay element and a time that corresponds to the occurrence of the identified signal peak. Delay versus frequency is characterized by isolating a segment of the obtained time domain reflection response that corresponds to a return signal from the reflective termination. Inverse frequency transforming the isolated segment of the time domain reflection response provides delay characteristics of the FTD versus frequency.

Abstract: A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge.

Abstract: A receiver that calculates the length of the transmission channel cable based on the receiver parameters is presented. The cable length is calculated based on the gain of an automatic gain control circuit or is based on the multiplier coefficients of an equalizer of the receiver. A comparison between a cable length calculated using the gain from the automatic gain control circuit and a cable length calculated using the multiplier coefficients of the equalizer indicates the quality of the cable.

Abstract: The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a “COMPARE” value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.

Abstract: Absolute delay of a FTD is characterized by applying a stimulus signal is applied to a first port of the FTD. A second port of the FTD is coupled to a delay element having a known delay and a reflective termination. A drive signal is applied to a third port of the FTD. A time domain reflection response to the stimulus signal is obtained and a signal peak within the response that corresponds to a return signal from the reflective termination is identified. Absolute delay of the frequency translation device is then extracted based on the known delay of the delay element and a time that corresponds to the occurrence of the identified signal peak. Delay versus frequency is characterized by isolating a segment of the obtained time domain reflection response that corresponds to a return signal from the reflective termination. Inverse frequency transforming the isolated segment of the time domain reflection response provides delay characteristics of the FTD versus frequency.

Abstract: A propagation delay time measuring method is provided that is capable of easily and accurately measuring propagation delay times Tb and Tc of a drive signal path BL1 connected between a driver DR1 and an I/O pin of an IC under test 119 and a response signal path BL2 connected between a comparator CP2 and the I/O pin of the IC under test, respectively, in a short time, wherein the drive signal path and the response signal path are formed to have the same length, a pulse is supplied to the drive signal path from the driver, and a timing when the pulse is outputted from the response signal path is detected, thereby to measure a total propagation delay time given to the pulse when the pulse has propagated through the drive signal path and the response signal path based on the detected timing, and a time duration equal to 1/2 of the measured propagation delay time is calculated and determined to be a propagation delay time of each of the drive signal path and the response signal path.

Abstract: The invention relates to a method for detecting at least one irregularity in the dielectric around a substantially elongate conductor, comprising of: applying a potential difference between the conductor and the earth; measuring at a first position voltage changes caused by said irregularity and moving in the direction of the first position; measuring at a second position voltage changes caused by said irregularity and moving in the direction of the second position; determining with the use of time registration the difference in arrival time of voltage changes caused by the same irregularity and measured at the first and second position; determining the position of the irregularity in said conductor on the basis of the, difference in arrival time and the length of said conductor between the first and second position.

Abstract: Absolute delay of a FTD is characterized by applying a stimulus signal to a first port of the FTD. A second port of the FTD is coupled to a delay element having a known delay and a reflective termination. A drive signal is applied to a third port of the FTD. A time domain reflection response to the stimulus signal is obtained and a signal peak within the response that corresponds to a return signal from the reflective termination is identified. Absolute delay of the frequency translation device is then extracted based on the known delay of the delay element and a time that corresponds to the occurrence of the identified signal peak. Delay versus frequency is characterized by isolating a segment of the obtained time domain reflection response that corresponds to a return signal from the reflective termination. Inverse frequency transforming the isolated segment of the time domain reflection response provides delay characteristics of the FTD versus frequency.

Abstract: A delay tracker utilizes a special code on the tracked signal in order to recognize such signal and ascertain any delays associated therewith.

Abstract: A method of and system for determining calibration offsets to account for delays introduced “downstream” of the reference driver (24) of a tester system (18) to test electronic components such as SRAM semiconductor memory devices. Such delays are created by, among other elements, receiver channels (30) of the tester system. A plurality of calibration modules (100) are provided, one for each receiver channel. Each calibration modules has a transmission line (110) with a known delay, a first contact 102′ and a second contact 102″. The tester system includes a socket (52) having a plurality of contactors (54) for contacting the reference clock contact and data output contacts of the electronic components undergoing test. The first contact of each calibration module is positioned to engage the contactor that engages the reference clock contact of the electronic component.