Abstract: A method for processing time-resolved optical emission data (“waveforms”) comprises processing both a first and a second waveform, and analyzing the results. The processing uses a substantial portion of the waveform and not merely the peaks of the waveform. A system which implements the method, and a computer readable medium which contains instructions for implementing the method, are also disclosed. The embodiments disclose methods for analyzing time-resolved optical emission data using correlation and/or transform techniques on the optical waveforms to extract timing information. The techniques offer more accurate results than direct examination of the waveforms and are additionally useful in tests having high noise or low numbers of detected photons. The techniques allow significant automation and the results lend themselves to graphic display.

Abstract: The invention accurately determines propagation delay for a sawtooth pattern. Through measurement, the actual delays added per bend in the sawtooth pattern are determined and the values are then used in a CAD tool. The invention can add a known amount of propagation delay to a wire length by routing net wires close together without using a large amount of board space.

Abstract: A reference length of electrically conductive material having a predetermined electrical length and impedance permanently inserted in a time domain reflectometer measuring path prior to the connection point to the cable-under-test. Measurement to the start of the reference length is used to establish a reference position within the measurement path for subsequent time domain reflectometry measurements.

Abstract: A circuit measures a signal propagation delay through a series of memory elements. In one embodiment the memory elements are configured in series so that together they form a delay circuit. In another embodiment the memory elements are configured in a loop to form a ring oscillator. Each memory element propagates a signal to a subsequent memory element so that the time the signal takes to traverse all of the memory elements is proportional to the average delay induced by the individual elements. This proportionality provides an effective means for measuring the delays of those components. Various embodiments of the invention measure the speeds at which memory elements can be preset, cleared, written to, read from, or clock enabled.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: A circuit measures a signal propagation delay through a series of memory elements on a programmable logic device. In one embodiment, a number of latches are configured in series. Each latch is initialized to store a logic zero. The first latch is then clock-enabled so that the output of the latch rises to a logic one. The logic one from the first latch clock-enables the second latch in the series so that the output of the second latch rises to a logic one, which in turn enables the next latch in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each latch to change in response to a clock-enable signal. Consequently, the delay through the series of latches provides a measure of the time required for one of the latches to respond to a clock-enable signal.

Abstract: A spectrum analyzer measures a time difference between two or more signals with different carrier frequencies or a time delay between two or more signals with the same carrier frequency. The spectrum analyzer includes at least two measurement channels, each of the measurement channels has a frequency mixer, a local oscillator and an IF (intermediate frequency) filter for mixing an input signal to be measured with a local signal of the local oscillator to produce an IF signal which passes through the IF filter, and a demodulator provided in one of the measurement channels to demodulate the IF signal produced from the input signal to generate a trigger signal to start an operation of the other measurement channel.

Abstract: A delay element testing apparatus has a signal generator for generating a plurality of signals, at least one of which is variable in timing; a phase comparator for making a comparison of a relationship in terms of phasic anteriority and posteriority between the signal passing through a delay element under test and the timing-variable signal among the plurality of signals; and a test result output circuit, controlled by a control signal generated by the phase comparator, for outputting a signal indicating a quality of a delay characteristic of the delay element under test. Main parts of this testing apparatus can be provided on a substrate to realize an integrated having a function for testing delay elements included therein.

Abstract: The phase response of a network is measured at uniform frequency intervals. A linear regression analysis is performed on samples of the phase response measured at frequencies within an aperture centered on a group delay frequency to obtain an estimate of the group delay of the network at that frequency. The process is repeated for a sequence of group delay frequencies to determine a trace of the group delay of the network across a range of frequencies.

Abstract: A method and an apparatus for testing compensated input/output buffers. In one embodiment, a compensated input/output buffer includes a node from which a plurality of compensation devices are coupled in parallel to a particular voltage level, such as for example V.sub.CC or ground. Compensation control signals are received by each one of the compensation devices such that the compensation signals are configured to selectively switch on and off each one of the plurality of compensation devices. An input/output test bus is coupled to the node and thus has access to each one of the compensation devices. Test circuitry is configured to selectively switch on and off each one of the compensation devices such that a switchable conductive path is formed from the node to the particular potential level through each one of the plurality of compensation devices.

Abstract: A wave shaping circuit for a semiconductor device testing apparatus reduces discrepancies in timing of signals by shortening lengths of signal transmission paths. The scale of the circuit is restrained by reducing the number of connecting lines between a modulation waveform generator and buffer circuits. A set signal and a reset signal generated by the modulation waveform generator are input to a first wave shaping SR register which produces a single pattern waveform to be applied to devices under test. The single pattern waveform is multiplied n-fold by the buffer circuit. Signals from the buffer circuit are received by invert/noninvert circuits which provide invert signals and noninvert signals. Differential circuits receive the invert/noninvert signals to generate set signals and reset signals having minimal discrepancies in timing which are input to second wave shaping SR registers.

Abstract: A delay time of a delay time generating circuit which delays an inputted pulse signal for a predetermined time and outputs the delayed pulse signal is measured. A random pulse generating circuit for outputting a train of pulses at random intervals is provided, and an output signal of the delay time generating circuit is applied to an input signal thereof through a positive feedback loop. An output signal is applied from the random pulse generating circuit to the positive feedback loop to cause the positive feedback loop to oscillate, and a delay time of the delay time generating circuit is determined from a period at which the positive feedback loop oscillates. The delay time can accurately be measured without being affected by an interference caused by another signal or a disturbance brought about by noise.

Abstract: Integrated circuits must fulfill published timing specifications that have been given to customers. To fulfill published timing specifications, such as minimum valid time and maximum valid time, a circuit for adjusting the output signals from an integrated circuit is introduced. The circuit comprises in part a speed detector circuit that determines the speed of a clock signal. The speed detector circuit outputs a speed signal that defines how fast the integrated circuit is operating. The speed signal is passed to a speed adjustment circuit. The speed adjustment circuit delays, as appropriate, output signals from the integrated circuit. The output signals are delayed such that output signals fulfill the timing, specifications published in the data book for this integrated circuit. The speed adjustment circuit delays output signals by adding buffers along the data path which add propagation delay to the output data path.

Abstract: A calibration method is provided for an IC tester which performs testing of ICs in association with a computer having a storage. A calibration file corresponding to results of calibration is stored by the computer. At first, the IC tester loads correction information representing results of a previous calibration from the computer. Then, a value of time propagation delay (TPD) is measured with respect to a pin selected from among pins of an IC and is compared with the correction information. The IC tester corrects a delay time provided for the pin whose value of TPD differs from the correction information. Thereafter, the correction information is renewed using the corrected delay time, so that the renewed correction information is stored by the computer. Thus, the IC tester completes the calibration prior to the testing of the IC.

Abstract: The present invention provides a simple circuit for measuring the delay time between a driver (DR) and a device under test (DUT), and the (DUT) and a comparator (CP) during the connection state of an I/O test where separate driver and comparator paths are used. In the connection circuit of the I/O test using two I/O common pins to connect to one of the pins of the DUT, a terminal pin of a DUT socket corresponding to the DUT pin is grounded. Furthermore, in the connection circuit of the I/O test using a DR-only pin and an I/O common pin to connect to the DUT pin, the terminal pin of the DUT socket is grounded and a standard comparator is employed.

Abstract: A relay test apparatus for testing a protective relay operation of a protective relay system comprises GPS receivers, respectively connected to the protective relays, each GPS receiver analyzing time data included in a signal transmitted from a satellite and outputting a time signal, simulation signal generators, respectively connected to the protective relays, each simulation signal generator generating a simulation signal and inputting the simulation signal to a corresponding protective relay, and synchronous starting units, respectively provided in the protective relays, each synchronous starting unit starting a corresponding simulation signal generator to generate the simulation signal, when time signals output from the GPS receivers coincide with a preset time at a same time.

Abstract: Radio waves having frequencies f.sub.1 and f.sub.2 are radiated to the premises where a wireless LAN is to be constructed. The radio waves of f.sub.1 and f.sub.2 are received by an antenna for scanning the observation plane and a fixed antenna, respectively. Then, the radio wave holograms of the respective radio waves are produced, from which are constructed radio wave source images separated into respective paths. The difference between these source images is found, and then the amplitude and the delay for each path are found. A propagation time response function x(t) of each path is found from the corresponding amplitude, delay and the directivity characteristics of the corresponding antenna, and then the real part and the imaginary part of each time response function are convoluted into a modulated carrier wave signal y(t). The convoluted results are multiplied by the in-phase component R.sub.f and the quadrature component R.sub.f.spsb.* of an unmodulated carrier wave, respectively.

Abstract: A method of measuring a delay time in a semiconductor device which has a particular circuit subject to delay time measurement, a test circuit coupled to an input terminal of the particular circuit for bypassing the particular circuit, and a selector for selectively outputting either an output signal from the particular circuit or an output signal from the test circuit.

Abstract: A returned reference compatible straightaway envelope delay measuring instrument and a related method use a sinewave generator to produce an envelope and a low frequency reference oscillator for modulating amplitude of the envelope. The low frequency modulated envelope signal is transmitted over a transmission path to an envelope detector, which detects the envelope. A phase detector connected to the envelope detector and to a local similar low frequency reference oscillator detects phase difference between the low frequency modulating oscillation in the envelope and a local reference oscillator signal. A processor makes a series of delay measurements and computes the delay difference between the start delay measurement and the end delay measurement.

Abstract: A relay test apparatus for testing a protective relay operation of a protective relay system comprises GPS receivers, respectively connected to the protective relays, each GPS receiver analyzing time data included in a signal transmitted from a satellite and outputting a time signal, simulation signal generators, respectively connected to the protective relays, each simulation signal generator generating a simulation signal and inputting the simulation signal to a corresponding protective relay, and synchronous starting units, respectively provided in the protective relays, each synchronous starting unit starting a corresponding simulation signal generator to generate the simulation signal, when time signals output from the GPS receivers coincide with a preset time at a same time.

Abstract: A circuit network measuring apparatus applies a measurement signal from a signal source to a device under test and measures circuit parameters of the device under test from the measurement signal and an output signal of the device under test. The apparatus includes a function which adds a frequency follow-up algorithm to a computer control portion to vary the output frequency of the signal source, thereby performing control such that the measured value will substantially equal a given value.

Abstract: According to the present invention, a process for use with automatic test equipment ("ATE") for determining a propagation delay in a semiconductor circuit is provided. In one embodiment of the invention, the process comprises the steps of determining an expected delay time by interpolating a first simulation capacitance, a second simulation capacitance, and an ATE capacitance, with a first simulated delay time and a second simulated delay time, the simulated delay times corresponding to the first and second simulated capacitances respectively, testing the semiconductor circuit with the ATE to determine an ATE delay time, and comparing the ATE delay time with the expected delay time to determine whether the propagation delay is acceptable.

Abstract: A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.

Abstract: A circuit and method for determining the operating performance of an integrated circuit which may be used to screen integrated circuits prior to sale or delivery, or to optimize the frequency of the integrated circuit during use. The circuit employs a comparison circuit to compare a first time of arrival of a clock pulse, which is propagating through the integrated circuit with a second time of arrival of the clock signal at a second input. The comparison circuit produces an output signal which may be used to reject or accept the integrated circuit, or to automatically adjust the frequency to minimize the delay.

Abstract: A test system for testing propagation delays of outputs of integrated circuit devices. The test system includes a test circuit for applying input signals to selected inputs of the digital integrated circuit and for sampling selected outputs of the digital integrated circuit, and respective loads for each of the selected outputs, each load having an impedance that is configured such that the sum of the specified internal delay for such output and a load dependent delay for such output comprise a total propagation delay that is substantially identical for all of the selected outputs, whereby all of the selected outputs are sampled simultaneously.

Abstract: A method and apparatus for measuring the settling time of frequency changes in a voltage controlled oscillator (VCO) are disclosed. A signal splitter is responsive to the VCO for splitting the output signal between first and second channels. A delay circuit in one of the channels introduces a delay and corresponding phase shift of one signal relative to the other, and a phase detector produces a phase signal proportional to the phase shift indicative of the settling time of the VCO. A control circuit coupled to the phase detector and the VCO produces a step voltage initiating signal for changing the VCO output frequency. A detector responsive to the initiating signal and the phase signal produces an output indicative of the settling time with respect to the control signal in the modulation domain.

Abstract: A calibration method and system for substantially reducing one of the components of timing error in automatic test systems. The timing associated with digital stimulus and response circuitry in a tester is different for positive and negative signal transitions. This inherent timing difference is normally measured and compensated for during the tester calibration process. The present method and system uses a short circuited transmission line as a pulse generator to achieve superior stability and accuracy when calibrating transition dependent timing in automatic test systems.

Abstract: A delay time measuring circuit includes a delay circuit for changing the delay times of first and second clock signals output to measure the delay time of an evaluated circuit according to an externally supplied control voltage, and a voltage controlled oscillator whose oscillation frequency is controlled by the same control voltage as that used for the delay circuit, and is constructed to measure the delay time of the evaluated circuit based on an output of the voltage controlled oscillator. Therefore, it is possible to precisely evaluate the operation speed of a circuit operating at high speed.

Abstract: The phase response of a network is measured at uniform frequency intervals. A linear regression analysis is performed on samples of the phase response measured at frequencies within an aperture centered on a group delay frequency to obtain an estimate of the group delay of the network at that frequency. The process is repeated for a sequence of group delay frequencies to determine a trace of the group delay of the network across a range of frequencies.

Abstract: Round trip absolute delays through a transmission system are measured. A modulation signal S1 of radian frequency .omega. is modulated onto a carrier. The modulation frequency is changed. While the change propagates through the system, the returned demodulated S2 signal remains at the old radian frequency .omega.. During that time, signal S1 advances in phase relative to signal S2. After the propagation time d which is equal to the network delay, the two signals stabilize at a fixed phase offset. The increase .theta..sub.o in the phase offset during the propagation time is determined. The delay d is then determined by dividing the phase offset increase .theta..sub.o by the difference between the two modulation frequencies.

Abstract: A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less.

Abstract: A method and apparatus for the measuring of a delay in a delay circuit by making a continuous frequency measurement is proposed. The phase-locking of a variable frequency signal applied to the delay circuit allows the user to significantly improve the precision and accuracy of the time delay measurement. A scheme to extract the number of cycles stored in the delay circuit is also disclosed.

Abstract: A pulse measuring instrument for measuring various pulse signal parameters such as the pulse width, the signal period of an input signal, and the time interval between input signals is capable of measuring the signal parameters with a high degree of accuracy and simplicity by automatically calibrating the propagation time difference between the input signal paths in the circuit configuration in the measuring instrument. The pulse signal measuring instrument is first provided with a calibration signal at the input terminal to obtain calibration data. The calibration data includes various time difference data regarding signal propagation time difference between the different signal paths in the measuring instrument. The calibration data also includes the signal period of the calibration signal and standard pulse width of the calibration signal. The calibration data is stored in a computer in the pulse signal measuring instrument.

Abstract: Apparatus and accompanying methods for inclusion in a Coriolis meter that substantially eliminate temperature induced measurement errors which might otherwise be produced by performance differences existing between the separate input channels contained in the meter. Specifically, two pairs of input channels are used in the meter. In operation, the meter repetitively measures the internal phase delay of each of these pairs and then subtracts the delay associated with each pair from actual flow based measurement data subsequently obtained therefrom. While one channel pair is measuring actual flow, the other channel pair is measuring its internal phase delay, with the channels being continuously cycled between these functions.

Abstract: A clock adjustment system for economically adjusting the output phases of a printed circuit board and an IC comprises a gate circuit for connecting an input of a measured circuit to an output. By turning the gate circuit on and by observing the oscillation of a measured circuit, the phase of the measured circuit is adjusted.

Abstract: By measuring the waveform of the reflected wave obtained by transmitting a pulse to an open-ended transmission line, a transfer function of the transmission line with respect to the incident wave is computed as a result of the measurement. Then, the waveform of the output wave at the output end or the open end of the transmission line is estimated in response to an individual input signal by using the transfer function computed. The transmission delay time of the transmission line is obtained by computing the time difference between the transient timing of the estimated waveform of the output wave and the transient timing of the waveform of the input signal.

Abstract: Periods P.sub.k between the one edges of input pulses are measured one after another by a successive period measuring circuit, and at the same time, the time interval between the one edge to the other of each input pulse, that is, a pulse width W.sub.k, is measured by a time interval measuring circuit. The measured periods are sequentially accumulated and each accumulated value is made to correspond to each pulse, as the time at which the measurement of its pulse width was started. In an interpolation part, pulse widths, which are assumed to be obtained at regular time intervals, are computed, by an interpolation method, from the sequence of measured pulse widths and the their measurement starting times. In a Fourier transform part, the pulse width data obtained by the interpolation is subjected to a Fourier transform to obtain the frequency components of a pulse width jitter.

Abstract: A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less.

Abstract: Method and apparatus for detecting a length of a cable connecting information equipments are disclosed. A reference signal which is a repetitively occurring signal is transmitted through a cable. A phase difference between the reference signal transmitted through the cable and the reference signal directly transmitted without routing the cable is detected, and a signal representing the cable length is produced based on the detected phase difference.

Abstract: The disclosure relates to the measurement of small time lags between a signal edge and a reference instant defined by another signal edge. It consists of the use of a signal edge for the prompting, by means of shock-excited resonating filters, of the appearance of two sinusoidal signals in quadrature constituting the components of a complex vector with a substantially constant module, the phase of said complex vector developing linearly in the course of time, and in deducing, from the value of this phase at the sampling reference instant, the value of the time lag between the reference instant and the signal edge. It can be applied more particularly to the measurement of short time lags of a few nanoseconds.

Abstract: A generator provides a repetitive pattern which is applied to the input of a DUT and to the input of a timing generator. The output of the DUT follows the pattern at the input, switching the voltage between two levels. The High Frequency Voltage Sampler measures instantaneous voltage levels on the output waveform of the DUT. The timing generator uses the input signal to generate enable signals for the High Frequency Voltage Sampler which are synchronized to the test waveform and which can be time-delayed in precise intervals and with good repeatability. By placing this signal at a desired point anywhere along the test waveform the voltage at this point can be measured by the High Frequency Voltage Sampler. The High Frequency Voltage Sampler uses the leading edge of the enable signal to start the measurement of the instantaneous voltage level and it uses the trailing edge to store this level.

Abstract: Apparatus and method for determining the electrical length of a signal flow path, such as a twisted-pair conductor, to create conductors of the same electrical length are disclosed. The term electrical length refers to a certain physical distance for a length of conductor for which an electrical signal travels, or propagates along the conductor, in a specified amount of time. The apparatus preferably includes a Time Domain Reflectometer 25 (including pulse generator means 30 and electrical response display means 20) which is cooperatively connected to a first end of a conductor pair 51 under test. The conductor pair 51 is inserted through a ground plane 60 or other impedance changing device. Means to mark or cut 62 the conductor 51 are located within the ground plane 60 or as close as possible to the point at which the impedance is changed. Processing means 40 are utilized to adjust the conductor 51 length relative to the ground plane 60.

Abstract: Settling time of an electrical device under test in response to a step wave input voltage is determined by first establishing first and second output voltage levels which differ from a settled output voltage level by preestablished voltage differentials, and then determining the time after applying a step wave voltage to the device under test when the output voltage equals the first and second voltages. A voltage controlled oscillator is utilized in triggering the step wave voltage generator and in enabling a voltage comparator whereby the period of the voltage control oscillator is a measure of the settling time of the device under test.

Abstract: Method and apparatus for detecting a length of a cable connecting information equipments are disclosed. A reference signal which is a repetitively occurring signal is transmitted through a cable. A phase difference between the reference signal transmitted through the cable and the reference signal directly transmitted without routing the cable is detected, and a signal representing the cable length is produced based on the detected phase difference.

Abstract: A PWM signal demodulation method measuring the leading edge period of a modulated signal and a time between adjoining leading and trailing edges of the signal and finding the modulation factor in terms of the ratio of the period to the time. Reliable demodulation is ensured even if the carrier frequency of the modulated signal varies significantly. This novel method eliminates one disadvantage of the prior art demodulation method encountered when a varying carrier frequency exceeds the linearity domain of an integrator in its integrating characteristic, causing unreliable demodulation.

Abstract: To determine the exact instant (T.sub.s) between the instant of transmission (T.sub.0) of the leading-edge of a square-wave pulse (S.sub.1) transmitted by a transmitter (4) and the instant (T.sub.1) of the first appearance of the received signal (S.sub.2), the latter is scanned with a threshold voltage (V) specifiable in steps, so that with n-time pulse transmission for repetition of the transmitting and receiving operation the threshold voltage is decreased by a value of .DELTA.V in each transmitting and receiving operation. The instantaneous value of the threshold voltage (V) is compared with the peak values (V.sub.A, V.sub.B, V.sub.C, V.sub.D) of the amplitudes of the positive half-waves of the received signal (S.sub.2). The instant at which the value of the threshold voltage (V) falls below the peak value (V.sub.A, V.sub.B, V.sub.C, V.sub.D) of the positive half-wave of the received signal (S.sub.

Abstract: Apparatus and a method for measuring average individual gate delays on integrated circuit wafers without the need for high bandwidth is provided. A chain of gates is provided on the wafer. A reference signal is propagated through the chain to produce a delayed signal. The delayed signal is logically combined with the reference signal to provide a periodic train of pulses whose period is proportional to that of the reference signal. The pulse widths represent the total gate delay of the chain, and are determined by statistically sampling the pulse train to determine its duty cycle. The apparatus and method are compatible with automated testing equipment and methods which can be synchronized with the reference signal.

Abstract: In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.

Abstract: Chip performance is measured using LSSD logic to propagate a signal through the LSSD scan path of the chip. The measurement data is compared to tabular data which is used to classify the AC chip performance. The use of the LSSD scan path provides an accurate overall measurement of an entire chip. The circuitry is internal to the system and does not require external test circuitry. No unique test patterns are required for a given chip design. The chip measurements can be made after installation of the chip in a field operational environment as well as during a manufacturing and testing environment. The chip measurements can be made by local execution of the testing or controlled from a remote location.

Abstract: A circuit for determining frequency response includes a voltage controlled oscillator (VCO) which generates a signal for application to a system under test and a counter which either counts quartz-stabilized pulses during a VCO period or which counts, during a quartz-stabilized counting interval, the VCO output itself. The counts represent with quartz accuracy the test frequency, which corresponds to the mean value within the counting interval, and are associated with respective measurement of signal level returned from the unit under test to thereby establish frequency response. Counts, together with corresponding levels developed by the system under test, are applied to a suitable display.