Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: An abnormality resulting from connection between a plurality of substrates is easily detected in a semiconductor device including a multilayer semiconductor substrate. The semiconductor device includes a plurality of semiconductor substrates, a connection member, a power supply terminal, and an observation terminal. The connection member is electrically connected on joint surfaces of the plurality of semiconductor substrates to form at least one connection line that extends over the plurality of semiconductor substrates. The power supply terminal is connected to one end of the connection line, and the observation terminal is connected to the other end of the connection line. Power is supplied to the power supply terminal. The observation terminal is used to observe a resistance state of the connection line.

Abstract: One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current.

Abstract: A dice testing method is provided. The dice testing method is used to determine which test data of test items can be explained by test data of other test items based on statistical analysis. After the test items with the test data that can be explained by the test data of the other test items are found out, corresponding dices will not be tested for those test items.

Abstract: A method is described. The method comprises determining a first measurement signal (CS1) which depends on a first load current (I1) through a first transistor (Q1) which is connected in series to a load (Z); determining a second measurement signal (CS2) which depends on a second load current (I2) through a second transistor (Q2) which is connected in series to the load (Z); and comparing the first measurement signal (CS1) and the second measurement signal (CS2), in order to detect the presence of an error.

Abstract: In an optical carrier injection method, a pulsed optical beam having pulse duration of 900 fs or lower is applied on a backside of a substrate of an integrated circuit (IC) wafer or chip, and is focused at a focal point in an active layer on a frontside of the substrate. Photons of the optical beam are absorbed at the focal point by nonlinear optical interaction(s) to inject carriers. The pulsed optical beam may be applied using a fiber laser in which the fiber is doped with Yb and/or Er. An output signal may be measured, comprising an electrical signal or a light output signal produced by the IC wafer or chip in response to the injected carriers. By repeating the applying, focusing, and measuring over a grid of focal points in the active layer, an image of the IC wafer or chip may be generated.

Abstract: The present disclosure provides a method, device and system for testing memory devices. The testing method includes: receiving a test instruction, the test instruction being used to characterize a model of a memory device to be tested that is connected to a test platform; selecting, according to the test instruction, a testing method corresponding to the model of the memory device to be tested from a plurality of pre-stored testing methods as a target testing method; and executing the target testing method to test the memory device to be tested.

Abstract: A method is for testing the functionality of a switching member including at least one switching element. A switching state is influenced via a control input of the switching element and via a control signal generated and output to the control input. An activation signal is output to the control unit and changes the control signal. The activation signal induces a test signal as the change to the control signal and induces a disconnection pulse as the test signal. The SiC or GaN power semiconductor is switched off via the disconnection pulse and conducts current in the reverse direction. In response to the disconnection pulse, the voltage drop is recorded. A comparison is carried out between an indicator and a reference encoding an expected response to the disconnection pulse. Depending on the result of the comparison, a status signal is generated which encodes the functionality of the switching member.

Abstract: Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.

Abstract: The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the ith stage being connected to fourth terminals of test units in the (i?1)th stage; wherein, the M and i are positive integers greater than or equal to 2.

Abstract: A display device is provided. A display device includes a display panel including a plurality of connecting signal wires which supply different control voltages; a flexible printed circuit board attached to a side surface of the display panel and including a base film and a plurality of lead wires which are disposed on the base film; an anisotropic conductive film disposed between the plurality of connecting signal wires and the plurality of lead wires, and at least one bump wire disposed between adjacent connecting signal wires, the at least one bump wire being not supplied with the different control voltages controlling the display panel.

Abstract: An automatic photocurrent spectrum measurement system based on a Fourier infrared spectrometer, including a light source component, an environment control component, a measuring module, and a control module. The system is configured to evaluate photoelectric performance semiconductor materials or devices under different temperatures, voltage biases or current biases.

Abstract: A probe apparatus for testing a semiconductor device is provided. The testing device includes a socket having a cavity for accommodating a device under test (DUT), and a cover disposed on the socket. The socket includes a thermal conductive material. The cover includes a plate, a circuit board attached to the plate, and an opening penetrating the plate and the circuit board, exposing the cavity of the socket.

Abstract: A ring oscillator circuit design includes three or more inverter stages connected in series. Each inverter stage includes one or more inverter devices including a PMOS device and a coupled NMOS device. The PMOS device in each of odd alternating inverter devices of the three or more inverter stages having a source terminal receiving power from a power rail conductor, and a source terminal of the coupled NMOS device in each of first alternating inverter devices is grounded. An output of a last inverter device of a last stage of the three or more inverter stages is connected to an input of a first inverter stage. The method measures a first frequency of a first ring oscillator circuit and measures a second frequency of a second ring oscillator circuit design to determine either a BTI or HCI failure mechanism of the first ring oscillator circuit based on the measurements.

Abstract: Systems and methods are provided for testing a threshold energy required to cause a latchup on an electronic component. An exemplary method includes applying a series of laser pulses to a testing object with a pulsed laser unit. The testing object is connected to a testing circuit which can measure the energy of each of the series of laser pulses, and detect whether a pulse of the series of laser pulses resulted in a latchup on the testing object. Upon detecting the pulse, the method provides for logging the energy of the pulse using a recording unit and logging the latchup status of the test device. If a latchup is detected, the testing circuit automatically mitigates the latchup event.

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

Abstract: A method for testing a memory chip includes: in response to read command for the memory chip, controlling clock signal to be kept in first state within first preset time period and at the same time controlling complementary clock signal to be kept in second state within first preset time period; in response to clock signal kept in the first state and complementary clock signal kept in the second state, keeping data strobe signal in the first state within second preset time period and at the same time keeping complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal and the complementary data strobe signal are kept in first and second states respectively, controlling first and second driving modules connected respectively to data strobe terminal and complementary data strobe terminal to operate and measure first and second resistance values respectively.

Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a plurality of memories and a first control circuit configured to control the plurality of memories. The first control circuit includes a first state transition circuit configured to execute at least one of write control and read control during an operation of the plurality of memories; and a second state transition circuit connected to the first state transition circuit, the second state transition circuit capable of causing the first state transition circuit to sequentially execute tests of the plurality of memories.

Abstract: An electronic component evaluation method is provided for evaluating an electronic component. The electronic component has a lower surface facing a mounting substrate, an upper surface having a flat main surface, and a plurality of mounting terminals configured to be mounted on the mounting substrate. The method includes the steps of: obtaining terminal position information of the plurality of mounting terminals; generating a reference plane including at least three of the plurality of mounting terminals in response to the terminal position information; and detecting a height of at least one of the upper surface or the lower surface relative to the reference plane.

Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.

Abstract: Embodiments of the present invention provide systems and methods for performing automated device testing at high power using ATI-based thermal management that substantially mitigates or prevents the pads and pins thereof from being burned or damaged. In this way, the lifespan of the testing equipment is improved and the expected downtime of testing equipment is substantially reduced, while also reducing cost of operation.

Abstract: A method includes placing a semiconductor device package in a test handler, the semiconductor device package having leads of a first portion of a package substrate extending from a mold compound and leads of a second portion isolated from the first portion extending from the mold compound; contacting the first portion with a first and a second conductive slug; contacting the second portion with a third and a fourth conductive slug; contacting a first surface of the mold compound with a first plunger having a conductive plate and an insulating tip; contacting an opposite second surface of the mold compound with a second plunger having a conductive plate and an insulating tip; and placing a high voltage on the first conductive slug while placing approximately half the high voltage on the conductive plate of the first plunger, and placing a ground voltage on the third conductive slug.

Abstract: An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.

Abstract: A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

Abstract: An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

Abstract: Circuits and methods encompassing a power converter that can be started and operated in a reversed unidirectional manner or in a bidirectional manner while providing sufficient voltage for an associated auxiliary circuit and start-up without added external circuitry for a voltage booster and/or a pre-charge circuit—that is, with zero external components or a reduced number of external components. Embodiments include an auxiliary circuit configured to selectively couple the greater of a first or a second voltage from a power converter to provide power to the auxiliary circuit. Embodiments include an auxiliary circuit configured to select a subcircuit coupled to the greater of a first or a second voltage from a power converter to provide an output for the auxiliary circuit. Embodiments include a charge pump including a gate driver configured to be selectively coupled to one of a first voltage node or second voltage node of the charge pump.

Abstract: The present disclosure provides a method of testing a testing device with a ground noise. The method includes coupling a device under test in series between a source and a ground in an automatic test equipment, coupling a ground bounce generator in series between the device under test and the ground, coupling the testing device to the device under test, providing a current by the source through the device under test and the ground bounce generator, controlling the ground bounce generator to generate the ground noise, and collecting a performance result of the testing device in the automatic test equipment.

Abstract: A method and apparatus related to developing electromagnetic emission and power models for a target device using photonic emissions thereof are provided. Data of photonic emissions of a target device during a first period of time with the target device in one or more modes is recorded. Data of electromagnetic emissions of the target device during the first period of time with the target device in the one or more modes is also recorded. The recorded data of the photonic emissions and the recorded data of the electromagnetic emissions are correlated to establish one or more electromagnetic emission models for the target device. The one or more electromagnetic emission models enable predictive analysis of emissions by the target device.

Abstract: An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.

Abstract: A switching module includes a switching unit and a determination unit configured to determine a function of the switching unit and an ON/OFF state of the switching unit. The switching unit is provided with a plurality of function determination resistors. The determination unit is configured to determine the function of the switching unit according to a combination of voltages applied to the plurality of function determination resistors corresponding to resistor values of the plurality of function determination resistors.

Abstract: Memory devices and systems with TSV health monitor circuitry, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies, a plurality of through-silicon vias (TSVs) in electrical communication with the memory dies; and circuitry. In some embodiments, the circuitry is configured to electrically couple a pair of TSVs of the plurality of TSVs to form a passive circuit. For example, the circuitry can activate a transistor electrically positioned between TSVs of the pair of TSVs to electrically couple the pair of TSVs. In these and other embodiments, the circuitry applies a test voltage to the pair of TSVs using the passive circuit to determine whether a TSV of the pair of TSVs includes degradation.

Abstract: A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.

Abstract: A test site and method are herein disclosed for predicting E-test structure (in-die structure) and/or device performance. The test site comprises an E-test structure and OCD-compatible multiple structures in the vicinity of the E-test structure to allow optical scatterometry (OCD) measurements. The OCD-compatible multiple structures are modified by at least one modification technique selected from (a) multiplication type modification technique, (b) dummification type modification technique, (c) special Target design type modification technique, and (d) at least one combination of (a), (b) and (c) for having a performance equivalent to the performance of the E-test structure.

Abstract: An on chip leakage-current detection device including a first inverter where the magnitude of delay of the output signal of the first inverter is determined by a leakage current of a target device. The leakage-current detection device further includes: a capacitor that is charged by the output signal of the first inverter; a second inverter coupled to capacitor that switches states when the capacitor is charged to a switching level; an odd number of additional inverters coupled in a sequence with a second-inverter output. The output of the leakage-current detection device has a frequency proportional to the leakage of the target device.

Abstract: Systems, methods, and computer program products directed to testing a System-in-a-Package (SIP) using an Automatic Test Equipment (ATE) machine. A functional representation of one or more tests to be performed in the SIP is loaded in a memory located on a load board, the load board located on the ATE machine. A test controller located on at least one of the SIP and the load board is caused to retrieve and store the one or more tests to be performed in the SIP. The test controller is instructed to conduct the one or more tests in the SIP.

Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.

Abstract: Physical or off-chip interfaces may be selectively bypassed in a boundary scan chain. A bypass control signal may be produced that indicates whether to bypass a selected one of the interfaces. In response to a first state of a bypass control signal, a multiplexer may couple the scan chain output of an interface boundary scan cell to the scan chain input of a successor boundary scan cell of the interface boundary scan cell. In response to a second state of the bypass control signal, the multiplexer may couple the scan chain output of a predecessor boundary scan cell of the interface boundary scan cell to the scan chain input of the successor boundary scan cell, bypassing the interface boundary scan cell.

Abstract: Disclosed are an IGBT-module condition monitoring equipment and method. The IGBT-module condition monitoring equipment includes an IGBT module, a gate turning-on voltage overshoot monitoring module, a driving circuit, a bond wire state judging module, and a signal acquisition module. The breakage condition of bond wires is obtained by comparing a monitored actual gate turning-on voltage overshoot with a preset reference gate turning-on voltage overshoot threshold. The present invention solves the problem encountered in monitoring the aging of IGBT bond wires in power electronic converters.

Abstract: An intermediary server receives a resource request from a client computer for a requested resource that has a desired resource ability to optimize the client computer. The intermediary server identifies an alternative resource that has the desired resource ability to optimize the client computer, and determines that an ability of the alternative resource to provide the desired resource ability exceeds an ability of the requested resource to provide the desired resource ability. In response to determining that the ability of the alternative resource to provide the desired resource ability exceeds the ability of the requested resource to provide the desired resource ability, the intermediary server instructs a resource server to send the alternative resource instead of the requested resource to the client computer.

Abstract: An approach for determining link transmission quality identifiers is provided. For this purpose, a two-step approach is applied. In a first step, quality indicators are obtained from a black-box device and related signal are obtained and recorded. Based on the recorded data, a model can be established or a neural network can be trained. The generated model or the trained network may be used for determining further quality indicators at any arbitrary point in time.

Abstract: The present invention is related to systems and methods for detecting an occluded object based on the shadow of the occluded object. In some examples, a vehicle of the present invention can capture one or more images while operating in an autonomous driving mode, and detecting shadow items within the captured image. In response to detecting a shadow item moving towards the direction of vehicle travel, the vehicle can reduce its speed to avoid a collision, should an occluded object enter the road. The shadow can be detected using image segmentation or a classifier trained using convolutional neural networks or another suitable algorithm, for example.

Abstract: A device includes a comparator, a reference signal node, a plurality of test signal nodes, and control logic. The reference signal node receives a reference signal. The reference signal node is coupled to a first input of the comparator. Each of the plurality of test signal nodes receives a corresponding test signal. The control logic is configured to initiate a comparison of each test signal to the reference signal via the comparator.

Abstract: Power control arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes an integrated circuit device comprising one or more processing cores and a power domain configured to distribute a supply voltage to the one or more processing cores. The assembly also includes a charge injection circuit coupled to the power domain of the integrated circuit device, and configured to selectively couple electric charge into the power domain to predictively offset at least portions of voltage transients in the power domain.

Abstract: An improved electric circuit structure for short circuit protection is applicable to examining a device under test, comprising a circuit breaking element, a thermistor, a filtering and rectifying module and a capacitor. A first end of the circuit breaking element is electrically connected to a power source. A first end of the thermistor is electrically connected to a ground. The filtering and rectifying module is connected between the second end of the circuit breaking element and the second end of the thermistor. The capacitor is connected to the filtering and rectifying module and in parallel with the device under test. The circuit breaking element disclosed in the present invention is a multi-protector fuse and forms an open circuit when the device under test forms a short circuit. Meanwhile, the multi-protector fuse is able to withstand voltage between its first and second end without generating any physical damage.

Abstract: A method and device for detecting a malicious circuit on an integrated circuit (IC) device is provided. The method includes generating a plurality of test patterns on the IC. A scan test circuit and the plurality of test patterns are used to test don't care bits of a function under test on the integrated circuit. Scan out data from the scan test circuit is provided in response to the plurality of test patterns. The scan out data is stored in a memory on the integrated circuit. The scan out data is monitored over a predetermined time period. If it is determined that a characteristic of the scan out data has changed within the predetermined time period, an indication that a malicious circuit has been detected is output. The device includes circuitry for performing the method in the field.

Abstract: A phase-locked loop (PLL) includes a voltage-controlled oscillator (VCO) that generates a PLL output signal having an oscillation frequency controlled by a control signal; a phase detector that generates a phase signal representing a difference in phase between the PLL output signal and a reference signal; a loop filter coupled to receive the phase signal; a switch; and a sampling circuit switchably coupled to receive the control signal of the VCO via the switch, and generating a code representing the control signal.

Abstract: Examples described herein include apparatuses and methods TSV resistance and short measurement in a stacked device. An example apparatus may include a chip comprising semiconductor substrate including a first surface and a second surface opposite to the first surface. The chip may include a first terminal formed above the first surface, a second terminal formed above the second surface, a buffer circuit coupled between the first and second terminals, a first through-substrate via (TSV) penetrating the semiconductor substrate, and a first switch coupled between the first terminal and the first TSV.