Abstract: A system, method and elliptic curve cryptography scheme having a fault injection attack resistant protocol. The cryptographic scheme has a first arithmetic operation having at least one of a single input bit, a single output bit, or a single output bit-string that is vulnerable to a fault injection attack. The protocol includes: performing a first arithmetic operation to determine a first output; performing a second arithmetic operation to determine a second output, the second arithmetic operation being a variant of the first arithmetic operation; and comparing the first output and the second output, and if the comparison is incompatible, outputting an invalidity condition, otherwise, outputting the first output.

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

Abstract: Apparatuses and methods for compensating for source voltage are described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.

Abstract: The present disclosure provides a system and method for switching firmware autonomously by a storage controller. The system and method include determining, by a switcher module of the storage controller, satisfaction of a debug condition based upon values of parameters of the debug condition. The debug condition is indicative of a problem within a storage system that includes the storage controller that facilitates communication between a host device and a non-volatile storage of the storage system. The system and method further include switching, by the switcher module, operation of the storage system from a primary firmware to a secondary firmware based upon the determination of the switcher module that the debug condition has been satisfied. The switching from the primary firmware to the secondary firmware occurs automatically without a switching request from the host device.

Abstract: A scan driver includes a plurality of signal lines configured to transfer a scan line selection signal for selecting a target scan line among a plurality of scan lines, and a plurality of logical elements respectively connected to some or all of a plurality of signal line groups respectively including grouped ones of the signal lines based on a combination calculation, the plurality of logical elements being respectively connected to the scan lines, and being configured to provide output signals to the scan lines, wherein a number of the signal line groups is greater than, or equal to, a number of the logical elements.

Abstract: Systems, apparatuses and methods related to subarray addressing for electronic memory and/or storage are described. Concurrent access to different rows within different subarrays may be enabled via independent subarray addressing such that each of the subarrays may serve as a “virtual bank.” Accessing the different rows as such may provide improved throughput of data values accessed from the respective rows being sent to a destination location. For instance, one such apparatus includes a plurality of subarrays within a bank of a memory device. Circuitry within the bank is coupled to the plurality of subarrays. The circuitry may be configured to activate a row at a particular ordinal position in a first subarray during a time period and a row at a different ordinal position in a second subarray of the plurality of subarrays during the same time period.

Abstract: A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.

Abstract: Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

Abstract: The present invention discloses a gate driving method of a pixel transistor and a gate drive circuit, as well as a display device including the gate drive circuit, which falls within the field of display technology. The method comprises the steps of: a gate drive circuit outputting a preset first voltage to a gate driving line of a pixel row prior to a transistor turn-on time of the pixel row, wherein the first voltage is greater than a transistor turn-off voltage; and the gate drive circuit outputting a transistor turn-on voltage to the gate driving line of the pixel row when it reaches the transistor turn-on time. Use of the present invention can improve the accuracy of pixel display.

Abstract: A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal.

Abstract: A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

Abstract: The drive capability of a logic circuit is improved. The logic circuit includes a first output node, a dynamic logic circuit, a diode-connected first transistor, and a capacitor. The dynamic logic circuit includes a second output node and a plurality of second transistors forming and evaluation circuit. The first transistor and the plurality of second transistors all have one of an n-type conductivity and a p-type conductivity. One terminal of the capacitor is electrically connected to the first output node. The other terminal of the capacitor is electrically connected to the second output node. A first terminal of the first transistor is electrically connected to the first output node. A first voltage is input to a second terminal of the first transistor. The voltage of the first output node is changed by a voltage applied to a back gate of the first transistor.

Abstract: Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

Abstract: Provided is a light-emission drive circuit that includes a power supply and a pull-up circuit. The power supply is configured to generate a voltage that is higher than a voltage in a controller. The controller is configured to supply a control signal that drives a light-emitting section. The pull-up circuit is provided between the power supply and an input terminal of the light-emission drive circuit, and includes a switching section configured to be turned on when a voltage of the input terminal is lower than a predetermined voltage. The predetermined voltage is lower than the voltage of the power supply.

Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

Abstract: A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A semiconductor device includes a 3-input NOR decoder having six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

Abstract: A power saving mode especially useful for memory decoders has been developed. At this power saving mode, the drain-to-source voltage of every MOS transistor in a memory decoder is set to zero, while at normal operation the memory decoder supports the same functions as prior art memory decoders.

Abstract: A semiconductor memory apparatus may precharge a plurality of word lines to first and/or second low voltages. The semiconductor memory apparatus may precharge an odd word line and an even word line to different levels, and accelerate passing GIDL occurring from a memory cell toward a word line to screen memory cells susceptible to GIDL.

Abstract: A column access control circuit for generating column write enable outputs with redundancy steering control and bit write control for an integrated circuit chip, and an integrated circuit chip having the same. A column access control circuit may include: a column write enable driver, a redundancy steering logic, and a bit write controller. The column write enable driver may produce column write enable outputs through an output. The column write enable driver is configured to receive certain column interleave write enable and enable column write according to the column interleave write enable received. The redundancy steering logic is configured to receive one or more fuses and skip a damaged column indicated by a corresponding fuse. The bit write controller is configured to receive one or more bit write and provide bit write control according to the one or more bit write received.

Abstract: Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second node and to decouple the first node from the second node, circuit blocks coupled to the second node and the switching circuit, and drivers coupled to the second node. Each of the circuit blocks includes a capacitor having a plate coupled to the second node. Each of the drivers is associated with a conductive line. The conductive line is associated with memory cells.

Abstract: An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.

Abstract: A display device has a data-holding circuit with a capacitance and a display portion with a plurality of pixel electrodes, formed on a first carrier substrate. In the display device, a second carrier substrate disposed opposite the first carrier substrate is placed above the display portion, but the opposing substrate is not present above the area in which the data-holding circuit is disposed. The parasitic capacitance of the data-holding circuit can thereby be reduced. Therefore, the capacitance in the data-holding circuit can be reduced and the area required can be reduced as well. The display data of all the pixels is sent serially to the liquid crystal module without high-speed transfer for each frame time interval, and size can be reduced because the controller IC and interface circuit are formed on the same substrate as the display device substrate.

Abstract: Provided is a technique that contributes to the improvement of voltage measurement accuracy and uniform current consumption of a battery in a voltage measurement device. Switch circuits (SWP and SWN) include switch elements (MP1 and MP2 or MN1 and MN2) which are provided between an input terminal and an output terminal, and switch driving units (401 to 409) which are driven between a first power supply voltage (VCC or GND) and a second power supply voltage (GND or VCC), which are different from each other, with an input voltage interposed therebetween.

Abstract: A method can be used for driving a switch circuit. The switch circuit includes a first transistor device and a second transistor device. Both the first transistor device and the second transistor device have a load path and a control terminal. The load paths of the first transistor device and the second transistor device are connected in series. The control terminal of the first transistor device is configured to receive a first drive signal and the control terminal of the second transistor device is configured to receive a second drive signal. One of an on-level switching on the first transistor device or an off-level switching off the first transistor device of the first drive signal is selected and one of a first signal level and a second signal level of the second drive signal is selected.

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract: Disclosed are a multi-functional integrated circuit and a source driver having the same. The integrated circuit (IC) chip includes: a first high-voltage transistor configured to precharge a storage node in response to a first control signal; a decoding unit configured to decode a plurality of input signals to output the decoded signal to the storage node; and a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal.

Abstract: Methods and apparatus for decoding of binary addresses and scanning rows and columns of an addressable array. In one example, an address decode circuit includes a first decoder circuit configured to partition an N-bit address into a plurality of address segments, each address segment including fewer than N bits, and N being a positive integer, the first decoder circuit configured to provide a plurality of first-stage decoded address outputs, and a second orthogonal decoder circuit coupled to the first decoder circuit and configured to receive the first-stage decoded address outputs and to produce 2N unique addresses from unique combinations of the plurality of first-stage decoded address outputs.

Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) an intermediate signal, and (ii) a clock signal. The second circuit may be configured to generate the intermediate signal and a digital complement of the output signal in response to (i) an input signal and (ii) the clock signal. The intermediate signal may form a feedback to ensure the output signal and the digital complement of the output signal are in complementary states during a power up.

Abstract: A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.

Abstract: A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: Logic circuits provide networks to simulate the functions of neural networks of the brain, and can discriminate degrees of state, and combinations of degrees of state, corresponding to a number of neurons. Logic circuits comprise Recursive AND NOT Conjunctions (RANCs), or AND NOT gates. A RANC is a general logic circuit that performs conjunctions for 2n possible combinations of truth values of n propositions. The RANCs function dynamically, with capabilities of excitation and inhibition. Networks of RANCs are capable of subserving a variety of brain functions, including creative and analytical thought processes. A complete n-RANC produces all conjunctions corresponding to the 2n possible combinations of truth values of n propositions.

Abstract: A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

Abstract: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and a drain which contact both ends of the channel layer. The driving transistor may be an enhancement mode transistor and the load transistor may be a depletion mode transistor.

Abstract: A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters boost the voltages of inputted signals to the voltages required by high voltage components and output the boosted signals. One of the first level shifters receives a first logic state and outputs a fifth logic state. Each of the other first level shifters receives a second logic state and outputs a sixth logic state. One of the second level shifters receives a third logic state and outputs a seventh logic state. Each of the other second level shifters receives a fourth logic state and outputs an eighth logic state. The demultiplexer outputs a ninth logic state and a plurality of tenth logic states according to the logic states outputted by the first level shifters and the second level shifters.

Abstract: A method for and the results of implementing a tree of multiplexing are disclosed. At each level of the tree, a sum-of-products or a product-of-sums representation is chosen to maximize inter-level optimizations.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4th) terminal (substrates/bodies) of MOSFET devices is implemented by the present invention to realize a novel decode personalization. The novel construction and operation of the decode personalization provides for maintaining body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a transistor moves inversely to its body potential, the body of each device is tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate, decode personalization and logical family operation.

Abstract: A logic gate includes a first driver to receive an input signal, and to control a connection between a first power source and a first node in correspondence with the input signal, a second driver coupled to the first node and a second power source, and to control a voltage of the first node, a third driver to control a connection between an output terminal and the first power source in correspondence with the voltage of the first node, a control transistor to control a connection between the third driver and the second power source, a fourth driver to control a connection between a gate electrode of the control transistor and the second power source, and a second capacitor between a first electrode of the control transistor and the gate electrode of the control transistor, wherein the transistors are a same type of MOS transistor.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Abstract: A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit.

Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.