Abstract: A buffer includes a pull-down means, a pull-up means, and a control signal generator. The pull-down means generates an output signal that transitions to a first state at a relatively high speed when an input signal transitions from a first state to a second state in response to a control signal at a first control state. The pull-up means generates an output signal that transitions to the second state at a relatively high speed when an input signal transitions from the second state to the first state in response to a control signal of a second control state. The control signal generator produces the control signal as a function of the output signal. Accordingly, the buffer can transfer an input signal at a high speed in both cases of a high-to-low transition of the input signal as well as a low-to-high transition of the input signal.

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches connected in series, the first switch being connected to an upper power supply and the third switch being connected to a lower power supply. The output of the circuit is connected to a circuit node located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit which provides a further output to control the first switch. The second switch is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage.

Abstract: A method and apparatus provides an efficient ratioed digital logic structure. The digital logic structure includes ratioed pull-up transistors and pull-down transistors such that the circuit noise margin does not substantially affect gain performance of the ratio stage. In one particular embodiment, a ratioed logic structure includes PMOS transistors and NMOS transistors that receive input voltage signals wherein a current path is induced in the NMOS transistors when a voltage input of zero or less is applied. Another feature of the present invention allows modification of gain performance of the ratio stage by arranging different ratios of the PMOS-to-NMOS transistor channel widths.

Abstract: A semiconductor integrated circuit which enables a subthreshold current to be suppressed when a logic gate circuit group is nonactivated and enables the logic gate circuit group to be activated at a high speed is provided. The semiconductor integrated circuit has at least one logic gate circuit connected to a feed line, a first transistor serially connected to the feed line in order to suppress the subthreshold current flowing in the logic gate circuit upon nonactivation of the logic gate circuit and a second transistor which is connected in parallel to the first transistor. The second transistor is activated prior to activation of the logic gate circuit and the first transistor.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device.

Abstract: An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.

Abstract: A semiconductor integrated circuit includes a pass transistor logic circuit and an output buffer. The output buffer compensates for an output level of the pass transistor logic circuit. Preferably, the output buffer includes a bootstrap circuit with a capacitor. The capacitor is preferably connected between a gate of an output transistor and an output terminal. Such an arrangement allows for the obtaining of a high voltage at the output terminal.

Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

Abstract: An output buffer with feedback to a predriver circuit such that the effective size of the predriver buffers are momentarily adjusted to favor a particular transition (i.e., low-to-high or high-to-low). The delayed output selectively alters the input threshold characteristic of the predriver circuit to favor the appropriate transition. Thus, the time during which the output drivers are subject to a crowbar current is reduced over previous devices.

Abstract: A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area.

Abstract: A driver for a signal line provides a desired pull-up voltage, different from a natural supply voltage, and desired terminating impedance. The driver forms a controllable split terminator voltage divider.

Abstract: A signal transition accelerating driver circuit firstly charges a signal line to a precharging level, thereafter, maintains the precharging level or discharges the signal line depending upon the potential level of the data/bus status signal, for this reason, any gate circuit is required, and the circuit configuration is simple.

Abstract: A buffer circuit including a pair of complementary P-channel transistor and N-channel transistor connected in series, the connecting point of which is connected to an output terminal. The gate terminal of the P-channel transistor is connected to a power supply when the input signal is a low level, and to the output terminal when the input signal is a high level. The gate terminal of the N-channel transistor is connected to the output terminal when the input signal is the low level, and to a ground when the input signal is the high level. This makes it possible to solve a problem of a conventional buffer circuit in that an increasing capacity of a load connected to an output terminal increases a delay time between a time the input signal changes to the high level and a time the output signal changes to the high level.

Abstract: A semiconductor integrated circuit includes a power supply circuit having a global source line VCC, a local source line QVCC coupled to VCC by a source switching transistor, and a global ground line VSS, a low-threshold logic (combinational) circuit connected between QVCC and VSS, and a data storage (sequential) circuit, connected between VCC and VSS. The data storage circuit includes a low-threshold input section for receiving data from the logic circuit and a high-threshold latch section for latching the data received by the input section. Mode switching transistors are inserted between the low-threshold logic circuit and VSS, between low-threshold input section and VCC and between the low-threshold input section and VSS, for effecting a sleep mode of the semiconductor integrated circuit. Low power dissipation is maintained with a reduced circuit scale.

Abstract: The semiconductor integrated circuit of this invention includes: a driver including a MOS transistor for driving a load; and a stabilizer for stabilizing a change in a voltage at a source of the MOS transistor due to a gate-source parasitic capacitance of the MOS transistor.

Abstract: An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which includes the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input composite transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node.

Abstract: A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: Alternately skewed gates to reduce signal transmission delay. For one embodiment, an integrated circuit includes a chain of gates alternately skewed for fast rise and fast fall. Pulse encoding logic coupled to the chain of gates pulse encodes a signal to be provided to and transmitted by the chain of alternately skewed gates.

Abstract: An array of multiple off chip drivers on an integrated circuit (IC) chip has reduced synchronous switching output timing error (TSSO) at high speeds of operation. The array includes a pair of low resistance buses to provide charge and discharge paths for the outputs, a plurality of terminals connecting the respective drivers between the buses, the resistance of each terminal being substantially greater than the resistance of either bus, and a plurality of capacitors connected internally of the respective drivers. Each driver has an input for receiving binary data from a memory unit and an output terminal which is switched in accordance with the binary input data to a higher or lower voltage level. There are a plurality of transistor switches within each driver which selectively couple a capacitor to the output terminal when it is driven high and at the same time couple another capacitor to one of the buses, and vice versa when the output terminal is driven low.

Abstract: A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

Abstract: A logic circuit output stage includes a first transistor with a first terminal that receives the first logic output signal and a third terminal coupled to a first output node. A second transistor has a first terminal coupled to the first terminal of the first transistor. A third transistor has a first terminal that receives the second logic output signal and a third terminal coupled to a second output node. A fourth transistor has a first terminal coupled to a third terminal of the second transistor and a second terminal coupled to the second output node. An impedance is connected between the third terminal of the second transistor and the first output node. In this output stage, the second transistor provides a transient signal to the first terminal of the fourth transistor in response to a transition in the first logic output signal. The fourth transistor provides a temporary change in the current flowing through the second output node in response to the transient signal received from the second transistor.

Abstract: Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay.

Abstract: A differential input circuit includes a first differential circuit of a current mirror type for generating a first differential voltage by using an input voltage and a reference voltage, a second differential circuit of a current mirror type for generating a second differential voltage having a phase opposite to that of the first differential voltage by using the input voltage and the reference voltage, and a third differential circuit for generating an output voltage corresponding to a difference voltage of the first and second differential voltages by using the first and second differential voltages. A first clamping circuit for clamping the first differential voltage is provided between the first and third differential circuits. A second clamping circuit for clamping the second differential voltage is provided between the second and third differential circuits.

Abstract: A programmable circuit is provided. The programmable circuit includes a programmable inverter circuit (PIC) that is configured to receive an input signal and to generate an output signal. The programmable circuit also includes a teaching circuit that is coupled to the PIC. The teaching circuit is configured to compare the output signal of the PIC to a desired output signal. Responsive to this comparison, the teaching circuit is configured to generate a control signal to the PIC. In response to the control signal the PIC is configured to generate the desired output signal.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: An inverter circuit has first and second input terminals for receiving a complementary input signals, first and second output terminals for outputting a complementary output signals generated from the complementary input signals, and a pair of rectifier sections each for flowing the charge stored on a higher-potential side of the output terminals to a lower-potential said of the output terminals, for saving power dissipation.

Abstract: A circuit, for processing high frequency digital signals minimizes radiation interference by reducing voltage swings at the circuit input. This is accomplished by forming circuit input structures, which exhibit very low input impedances. An example of such input circuitry is a common gate amplifier with a diode coupling the source electrode of the common gate amplifier to ground potential and input signal applied to the source electrode. Output signal is derived from the collector of the common gate electrode which has a further diode as a load circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: A logic circuit having at least a first input terminal and at least a first output terminal, comprises at least a first and a second electron-wave Y-branch switch, each having a source, a first drain, a second drain, and at least a first gate for switching a source current between the first and the second drain. The sources of said first and second Y-branch switches are adapted to be connected to a high voltage supply and a low voltage supply, respectively. The first gates of said first and second Y-branch switches are interconnected, and the interconnection point between said first gates constitutes said first input terminal. The first drain of the first Y-branch switch is connected to the second drain of the second Y-branch switch, and the second drain of the first Y-branch switch is connected to the first drain of the second Y-branch switch.

Abstract: A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor.

Abstract: A circuit for accelerating digital signal transitions includes an input/output node to receive a digital input signal. A transition termination circuit is connected to the input/output node to generate a transition termination signal when the digital input signal approaches a final signal level. A transition acceleration circuit is connected to the input/output node and the transition termination circuit. The transition acceleration circuit is activated to accelerate the digital input signal to a full digital signal level when the digital input signal achieves an initial signal transition level and is deactivated when the transition termination signal is received.

Abstract: An improved line driver is disclosed. In one embodiment, the line driver has three inverters and a pass gate. The first inverter has a first input terminal connected directly to the input line of the line driver. The first inverter also has an output terminal coupled to a first output line of the line driver. The second inverter has an output node coupled to a second output line of the line driver. The third inverter has a first input terminal connected directly to the input line of the line driver and an output terminal coupled to the input node of the second inverter. The pass gate has a second input terminal coupled to the input line of the line driver and an output terminal coupled to both the second input terminal of the first inverter and the second input terminal of the third inverter. The pass gate receives an enable signal at a first input terminal and provides a conduction path between the input line of the line driver and the output terminal of the pass gate in response to the enable signal.

Abstract: Logic books with mixed low V.sub.t and regular V.sub.t devices provide a performance gain without the large increase in stand-by power of the logic book. Low V.sub.t devices are used to gain speed, and regular V.sub.t devices are used to cut off the off-current of the logic book. The optimization of mixed V.sub.t configurations is important. No single path between an output and ground can be made of all low V.sub.t devices, and no single path between the output and V.sub.dd can be made of all low V.sub.t devices. Generally, devices that are connected to V.sub.dd and ground should be regular V.sub.t devices, a low V.sub.t devices should be connected closest to the output. All low V.sub.t devices should be appropriately reversely biased in their off states. Because its merits in standby power, speed and noise margin, such mixed-low-and-regular-V.sub.t logic books can have a wide use in VLSI designs (e.g., high performance microprocessor design).

Abstract: An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

Abstract: A method and apparatus for improving the forward path switching speed of a complementary CMOS inverter is presented. A large P-type to N-type FET ratio is used to tune the inverter trigger point to the falling edge of the input signal to the inverter. The high P-type to N-type ratio is made feasible by adding a precharge assist pull-down transistor in parallel on the output node of the inverter.

Abstract: A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.

Abstract: A circuit and method for providing a fast transitioning output buffer that may be configured to operate using either a 3 volt or 5 volt supply voltage. The pullup behaves similarly to a MOS diode, but the circuit lowers the gate voltage on a pullup while the output is being pulled up. The circuit does not affect the final pullup voltage. As a result, a single PMOS device may be used as a pullup device that does not generally require an increased size to support a high operating voltage.

Abstract: A high-speed dynamic logic circuit having a high tolerance to noise includes pMOS and nMOS transistors constructing a buffer, which is connected to an internal dynamic node, for driving an output terminal. Only the pMOS transistor, which operates in an evaluation cycle, is connected to the dynamic node. The nMOS transistor is driven by a signal that is the inverse of a precharge signal. A weak latch, or an nMOS transistor of minimum size driven by the dynamic node, is connected to the output terminal as a leakage compensation circuit.

Abstract: A power reduction circuit is provided that includes a first switching device between a first operating voltage terminal and a second operating voltage terminal being controlled by a first active signal. A second switching device is between a third operating voltage terminal and a fourth operating voltage terminal is controlled by the inverse active signal. A signal transfer gate logic coupled between the second and the fourth operating voltage terminals to selectively output one of the second and the fourth operating voltages. A first voltage drop device is between the first and the second operating voltage terminals and is selectively activated by a first control device according to one of a first and a second operating modes. A second voltage drop device is between the third and the fourth operating voltage terminals and is selectively activated by a second control device according to one of the first and the second operating modes.

Abstract: A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node (26.sub.PN, 28.sub.PN, 30.sub.PN) to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path (26.sub.L and 26.sub.DT, 28.sub.L and 28.sub.DT, 30.sub.L and 30.sub.DT) conrected to the precharge node Each discharge path is operable in response to at least one enabling input signal (INPUTS.sub.26, INPUTS.sub.28, INPUTS.sub.30) to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter (26.sub.INV, 28.sub.INV, 30.sub.INV) coupled to the precharge node and having an output for providing a second monotonic transitioning data signal.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met.

Abstract: Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic meaning. Threshold values may be equal to or less than the number of input signal lines. Threshold gates switch their outputs from NULL to a meaningful state when the threshold number of inputs assume meaningful states. Gates will hold outputs in a meaningful (or non-null) state when the number of asserted inputs remains positive, even if the number is less than the threshold. In one embodiment, threshold gates include a "FLASH" input that forces the gate to NULL. In another embodiment, threshold gates include one or more "SET" inputs that drive the gate output to NULL or to a meaningfull state.

Abstract: A static pass-transistor logic gate design which incorporates the new technique of forecasted-restoration of the output logic-level. The forecasting of the need for output logic-level restoration is accomplished by the connection of restoration circuit inputs to a logic-gate input, which provides the appropriate logic input signal to the restoration circuit, to properly control the state of the restoration circuit. Logic gate inputs which are unnecessary in the determine of the appropriate restoration circuit input logic state are connected to the appropriate input logic levels. Further, there is potential for significant area savings, with accompanying economic benefit when using the FRCPG logic, due to the reduced transistor count of FRCPG.

Abstract: A buffer having first and second input terminals and an output terminal. The buffer also includes a fast edge driver having an input terminal and an output terminal, with the input terminal connected to the first input terminal of the buffer, and the output terminal connected to the output terminal of the buffer. A shielding circuit is provided having an input terminal and an output terminal, with the input terminal connected to the second input terminal of the buffer. The buffer further includes a recovery circuit having an input terminal and an output terminal, with the input terminal connected to the output terminal of the shielding circuit, and the output terminal connected to the output terminal of the buffer.

Abstract: An output buffer control circuit is provided in which a three-phase (state) level of an output warning can be realized in a short time, which results in increasing the processing speed. The output buffer control circuit uses a predetermined width pulse at the point when the output control signal is changed to low level. The predetermined width pulse is operated with the previous output signal and the resultant signal feeds back to the output terminal.